From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1M7uFj-00036e-1u for qemu-devel@nongnu.org; Sat, 23 May 2009 12:39:19 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1M7uFh-00035o-2D for qemu-devel@nongnu.org; Sat, 23 May 2009 12:39:18 -0400 Received: from [199.232.76.173] (port=33310 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1M7uFg-00035j-Tq for qemu-devel@nongnu.org; Sat, 23 May 2009 12:39:16 -0400 Received: from flounder.pepperfish.net ([87.237.62.181]:50751) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1M7uFg-0005z6-B9 for qemu-devel@nongnu.org; Sat, 23 May 2009 12:39:16 -0400 Received: from [10.112.102.2] (helo=jennifer.kylikki.org) by flounder.pepperfish.net with esmtps (Exim 4.69 #1 (Debian)) id 1M7uFb-0004jI-Rh for ; Sat, 23 May 2009 17:39:11 +0100 Received: from derik.kyllikki.org ([192.168.7.20] helo=derik) by jennifer.kylikki.org with esmtp (Exim 4.69) (envelope-from ) id 1M7uFe-0000Xj-Lx for qemu-devel@nongnu.org; Sat, 23 May 2009 17:39:14 +0100 Received: from vince by derik with local (Exim 4.69) (envelope-from ) id 1M7uFe-0005vl-KD for qemu-devel@nongnu.org; Sat, 23 May 2009 17:39:14 +0100 Date: Sat, 23 May 2009 17:39:14 +0100 From: Vincent Sanders Subject: Re: [Qemu-devel] [PATCH 02/15] S3C system on chip integrated peripheral device state header Message-ID: <20090523163914.GB8037@derik> References: <1241599494-28654-1-git-send-email-vince@simtec.co.uk> <1241599494-28654-3-git-send-email-vince@simtec.co.uk> <20090515223312.GM16288@game.jcrosoft.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090515223312.GM16288@game.jcrosoft.org> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Sat, May 16, 2009 at 12:33:12AM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote: > > + uint32_t tclk1; /* second timer clock source frequency */ > > + > > + /* GPIO block */ > > + uint32_t gpio_reg[47]; > > + > > + /* Realtime clock */ > > + uint8_t rtc_reg[19]; > > + > > + /* i2c */ > > + struct s3c24xx_i2c_state_s *iic; > > + > > + /* Timers, (Specifically timer4) */ > > + uint32_t timers_reg[17]; > it will be better to define a struct with the timers_reg content > same with the other arry I had a good hard look at this and decided you were right. I have restructured all the SOC devices to be completely self contained. I just posted the new series against git head, it looks a fair bit neater. -- Regards Vincent http://www.kyllikki.org/