From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MB5nX-0002CI-AG for qemu-devel@nongnu.org; Mon, 01 Jun 2009 07:35:23 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MB5nR-0002Bj-AM for qemu-devel@nongnu.org; Mon, 01 Jun 2009 07:35:21 -0400 Received: from [199.232.76.173] (port=50446 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MB5nR-0002Bg-7c for qemu-devel@nongnu.org; Mon, 01 Jun 2009 07:35:17 -0400 Received: from mail2.shareable.org ([80.68.89.115]:59076) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MB5nQ-0003Hz-S9 for qemu-devel@nongnu.org; Mon, 01 Jun 2009 07:35:17 -0400 Date: Mon, 1 Jun 2009 12:35:12 +0100 From: Jamie Lokier Subject: Re: [Qemu-devel] Add ARM920T to ARM emulation Message-ID: <20090601113512.GA16957@shareable.org> References: <1243603405-12989-1-git-send-email-vince@simtec.co.uk> <200905292305.28740.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905292305.28740.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: Vincent Sanders , qemu-devel@nongnu.org Paul Brook wrote: > > There was some discussion of the differences between v4 and v5 with > > respect to LDR behaviour manipulating the program counter when the > > bottom bit of an adress is set. The ARM-ARM clearly defines such > > behaviour as "unpredicatble" (section A2.4.3 page 48) where it says > > "In all variants of ARMv4 and ARMv5, bits[1:0] of a value written to > > R15 in ARM state must be 0b00. If they are not, the results are > > UNPREDICTABLE." . > > This statement is only applies to instructions that do not have explicit > semantics for r15. Use of r15 as a destination in load/pop instructions is > well defined. I notice that ARMv4T adds the BX instruction, implying that B isn't able to switch to Thumb mode although it can in later architectures (I never saw the point in BX, and I guess ARM ended up the same :-) Is the behaviour defined to _not_ switch to Thumb when using B to an address with the low order bit set, or does it trap, or is it unpredictable? (While we're here, I would quite like to see the distinction between ARMv4 and ARMv4T for testing of userspace interworking code, but I'll add that myself if I need it - as far as I know, the difference would just be BX/BLX being an illegal instruction, and low-order bit in R15 being ignored.) -- Jamie