From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MBGf6-000183-OF for qemu-devel@nongnu.org; Mon, 01 Jun 2009 19:11:24 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MBGf2-00017b-A4 for qemu-devel@nongnu.org; Mon, 01 Jun 2009 19:11:24 -0400 Received: from [199.232.76.173] (port=57649 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MBGf2-00017Y-5E for qemu-devel@nongnu.org; Mon, 01 Jun 2009 19:11:20 -0400 Received: from mail2.shareable.org ([80.68.89.115]:33761) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MBGf0-0007Fi-Vc for qemu-devel@nongnu.org; Mon, 01 Jun 2009 19:11:19 -0400 Date: Tue, 2 Jun 2009 00:11:15 +0100 From: Jamie Lokier Subject: Re: [Qemu-devel] Add ARM920T to ARM emulation Message-ID: <20090601231115.GC28406@shareable.org> References: <1243603405-12989-1-git-send-email-vince@simtec.co.uk> <200905292305.28740.paul@codesourcery.com> <20090601113512.GA16957@shareable.org> <200906011313.49802.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200906011313.49802.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: Vincent Sanders , qemu-devel@nongnu.org Paul Brook wrote: > > I notice that ARMv4T adds the BX instruction, implying that B isn't > > able to switch to Thumb mode although it can in later architectures (I > > never saw the point in BX, and I guess ARM ended up the same :-) > > > > Is the behaviour defined to _not_ switch to Thumb when using B to an > > address with the low order bit set, or does it trap, or is it > > unpredictable? > > You need to look again at the B instruction. Hopefully then you'll realise why > you're talking nonsense. Ach, sorry. My head's been buried in FDPIC, where BX is only used on ARMvT; on everything else, LDR/LDM does the job. So I inconveniently forgot what you cluebricked me about. > loads into the PC either ignore(v4t) or mode switch (v5) on the low > address bit. ALU writes to the PC always ignore the low bit in > Thumb mode. In ARM mode the low bit is either ignored(v6) or used to > mode switch (v7). Thanks, it's what I've found too. from reading the 2005 ARM ARM just now. I'll add that ARM-mode ALU writes to the PC on (v4/v4t/v5) (and loads on v4/v4t), "bits[1:0] must be 0b00, if they are not, the results are UNPREDICTABLE". Whereas for (v6), the bits are ignored, and as you say for (v7) the least-significant bit is meaningful. -- Jamie