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Date: Wed, 03 Jun 2009 09:34:02 -0600 (MDT)
Message-Id: <20090603.093402.2073897480.imp@bsdimp.com>
Subject: Re: [Qemu-devel] [PATCH] fix configure for mips o32
From: "M. Warner Losh" <imp@bsdimp.com>
In-Reply-To: <87ws7ttkch.fsf@lechat.rtp-net.org>
References: <87prdlv6wf.fsf@lechat.rtp-net.org>
	<200906031546.00539.paul@codesourcery.com>
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To: arnaud.patard@rtp-net.org
Cc: paul@codesourcery.com, qemu-devel@nongnu.org

In message: <87ws7ttkch.fsf@lechat.rtp-net.org>
            Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> writes:
: Paul Brook <paul@codesourcery.com> writes:
: 
: > On Wednesday 03 June 2009, Arnaud Patard wrote:
: >> The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining
: >> target_phys_bits and set it to 64 for all mips machines including mipsel
: >> machines which are 32 bit. This patch set it to 32.
: >
: > MIPS32 CPUs have a 36-bit physical address space. That's what the old code 
: > said anyway.
: 
: Is there more information than that in the old code ? I really thought
: mips32 4Kc have 32-bit address paths not 36.

Are you talking virtual addresses or physical addresses?  arc machines
are little endian and have 36-bit physical addresses because they are
based on the r4400 processors.  And much of the hardware is located
above 4GB, so needs to be accessed through special TLB entries.

Of course, this is orthogonal to my original point: mipsel and mips
specify the endian of the machines, not the underlying size.

Warner