From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MCTta-0002ec-2L for qemu-devel@nongnu.org; Fri, 05 Jun 2009 03:31:22 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MCTtV-0002bp-9S for qemu-devel@nongnu.org; Fri, 05 Jun 2009 03:31:21 -0400 Received: from [199.232.76.173] (port=54280 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MCTtV-0002bg-5A for qemu-devel@nongnu.org; Fri, 05 Jun 2009 03:31:17 -0400 Received: from mx20.gnu.org ([199.232.41.8]:49972) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MCTtT-0003wA-Kp for qemu-devel@nongnu.org; Fri, 05 Jun 2009 03:31:17 -0400 Received: from bsdimp.com ([199.45.160.85] helo=harmony.bsdimp.com) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MCTtJ-000750-4j for qemu-devel@nongnu.org; Fri, 05 Jun 2009 03:31:05 -0400 Date: Fri, 05 Jun 2009 01:29:32 -0600 (MDT) Message-Id: <20090605.012932.-1325212215.imp@bsdimp.com> Subject: Re: [Qemu-devel] [PATCH] fix configure for mips o32 From: "M. Warner Losh" In-Reply-To: <87r5y0tkzg.fsf@lechat.rtp-net.org> References: <87ws7ttkch.fsf@lechat.rtp-net.org> <200906031622.48342.paul@codesourcery.com> <87r5y0tkzg.fsf@lechat.rtp-net.org> Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: arnaud.patard@rtp-net.org Cc: paul@codesourcery.com, qemu-devel@nongnu.org In message: <87r5y0tkzg.fsf@lechat.rtp-net.org> Arnaud Patard (Rtp) writes: : Paul Brook writes: : : Hi, : : > On Wednesday 03 June 2009, Arnaud Patard wrote: : >> Paul Brook writes: : >> > On Wednesday 03 June 2009, Arnaud Patard wrote: : >> >> The commit 1ad2134f914dfd4c8f92307c94c9a5a1e28f0059 is defining : >> >> target_phys_bits and set it to 64 for all mips machines including mipsel : >> >> machines which are 32 bit. This patch set it to 32. : >> > : >> > MIPS32 CPUs have a 36-bit physical address space. That's what the old : >> > code said anyway. : >> : >> Is there more information than that in the old code ? I really thought : >> mips32 4Kc have 32-bit address paths not 36. : > : > I suspect you're confusing physical and virtual addresses. : > : : fwiw, found out where I read that. At : http://www.mips.com/products/processors/hard-ip-cores/4kc-hard-ip-core/. None-the-less, mipsel for arc has 36-bit addresses. The patch is bad. Warner