From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MGcdA-0006wh-1R for qemu-devel@nongnu.org; Tue, 16 Jun 2009 13:39:32 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MGcd5-0006sY-Ad for qemu-devel@nongnu.org; Tue, 16 Jun 2009 13:39:31 -0400 Received: from [199.232.76.173] (port=51528 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MGcd4-0006sR-VS for qemu-devel@nongnu.org; Tue, 16 Jun 2009 13:39:27 -0400 Received: from mx2.redhat.com ([66.187.237.31]:36048) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MGcd4-0007zf-BR for qemu-devel@nongnu.org; Tue, 16 Jun 2009 13:39:26 -0400 Date: Tue, 16 Jun 2009 20:37:23 +0300 From: Gleb Natapov Subject: Re: [Qemu-devel] [PATCH] Register usb-uhci reset function. Message-ID: <20090616173723.GF782@redhat.com> References: <20090616124702.GS19508@redhat.com> <200906161814.58491.paul@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200906161814.58491.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paul Brook Cc: qemu-devel@nongnu.org On Tue, Jun 16, 2009 at 06:14:57PM +0100, Paul Brook wrote: > On Tuesday 16 June 2009, Gleb Natapov wrote: > > Update irq line on reset. Reseting irq line is required because > > racing irq from pci device will call piix3_set_irq(). piix3_set_irq() > > will remember current level in pci_irq_levels[]. The PIC line will be > > triggered if one of pci_irq_levels[] is set (depends on piix3 config). > > If for instance pci_irq_levels[0] and pci_irq_levels[1] are mapped to > > the same PIC irq and during reset pci_irq_levels[1] == 1, but device > > that drives pci_irq_levels[0] is initialized first the device driver > > will not be able to lower irq line. > > This is nonsense. > The writeup below is nonsense. I described you circumstances. Show me the code where it works different from what I described. > The only relevant circumstances are if the devices raises an IRQ, and is then > reset by software while the system is running. It's got nothing to do with > piix3, PCI bus interrupt sharing or system reset. If you are seeing problems > after a system reset then your bug lies elsewhere. > So you apparently never heard about hardware reset? You never saw buggy guests that does not reset HW before reboot? -- Gleb.