From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MGcFX-0004Jb-9H for qemu-devel@nongnu.org; Tue, 16 Jun 2009 13:15:07 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MGcFS-0004Hz-F1 for qemu-devel@nongnu.org; Tue, 16 Jun 2009 13:15:06 -0400 Received: from [199.232.76.173] (port=47574 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MGcFS-0004Hs-7r for qemu-devel@nongnu.org; Tue, 16 Jun 2009 13:15:02 -0400 Received: from mx20.gnu.org ([199.232.41.8]:47161) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MGcFS-0003a5-0m for qemu-devel@nongnu.org; Tue, 16 Jun 2009 13:15:02 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MGcFR-0002yE-1s for qemu-devel@nongnu.org; Tue, 16 Jun 2009 13:15:01 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] Register usb-uhci reset function. Date: Tue, 16 Jun 2009 18:14:57 +0100 References: <20090616124702.GS19508@redhat.com> In-Reply-To: <20090616124702.GS19508@redhat.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906161814.58491.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Gleb Natapov On Tuesday 16 June 2009, Gleb Natapov wrote: > Update irq line on reset. Reseting irq line is required because > racing irq from pci device will call piix3_set_irq(). piix3_set_irq() > will remember current level in pci_irq_levels[]. The PIC line will be > triggered if one of pci_irq_levels[] is set (depends on piix3 config). > If for instance pci_irq_levels[0] and pci_irq_levels[1] are mapped to > the same PIC irq and during reset pci_irq_levels[1] == 1, but device > that drives pci_irq_levels[0] is initialized first the device driver > will not be able to lower irq line. This is nonsense. The only relevant circumstances are if the devices raises an IRQ, and is then reset by software while the system is running. It's got nothing to do with piix3, PCI bus interrupt sharing or system reset. If you are seeing problems after a system reset then your bug lies elsewhere. Paul