From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MGcxK-0006JA-TU for qemu-devel@nongnu.org; Tue, 16 Jun 2009 14:00:22 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MGcxG-0006Fr-0H for qemu-devel@nongnu.org; Tue, 16 Jun 2009 14:00:22 -0400 Received: from [199.232.76.173] (port=48089 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MGcxF-0006Ff-EZ for qemu-devel@nongnu.org; Tue, 16 Jun 2009 14:00:17 -0400 Received: from mx20.gnu.org ([199.232.41.8]:48923) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MGcxF-0003Ah-2S for qemu-devel@nongnu.org; Tue, 16 Jun 2009 14:00:17 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MGcxD-0005NI-6f for qemu-devel@nongnu.org; Tue, 16 Jun 2009 14:00:15 -0400 From: Paul Brook Subject: Re: [Qemu-devel] Register uhci_reset() callback. Date: Tue, 16 Jun 2009 19:00:10 +0100 References: <20090611084808.GA19508@redhat.com> <200906161754.59643.paul@codesourcery.com> In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906161900.11811.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Avi Kivity , Gleb Natapov > > Devices should not cause IRQ state changes on restore. Commit 3dcd219f > > is incorrect. > > I'm not so sure about this, but I can't think of a restore sequence > where the IRQ state would need to be changed if the IRQs tied together > are handled correctly. But surely if the devices states are restored > in strange order, the state changes could cause problems because the > device receiving the IRQ may still contain old state. It's precisely because devices are restored in unpredictable order that they should not be communicating with other devices (e.g. by modifying IRQ lines). Consider a system with a device (DEV) and a level triggered interrupt controller (PIC1) chained to an edge triggered interrupt controller (PIC2). (DEV) -> (PIC1) -> (PIC2) Before restore, DEV output is low, PIC1 has the interrupt unmasked (but low), PIC2 has no pending interrupts. We now restore a state where DEV output is high, PIC1 has masked the interrupt, and PIC2 has no pending interrupts. Devices are restored in he order PIC2, DEV, PIC1. If devices toggle their interrupts on restore then we get incorrect state after the restore: PIC2 is restored to the desired no-interrupts-pending state. DEV is restored. This raises the IRQ, which is passed to PIC1. PIC1 still has the old interrupt mask, so passes through to PIC2, which detects the edge event and marks the interrupt as pending. PIC1 is restored, updates the new mask and lowers its output. However this does not clear the internal PIC2 pending interrupt flag, so machine state will be wrong after resume. Paul