From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MGeI3-0004dq-U7 for qemu-devel@nongnu.org; Tue, 16 Jun 2009 15:25:51 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MGeHz-0004Yy-3L for qemu-devel@nongnu.org; Tue, 16 Jun 2009 15:25:51 -0400 Received: from [199.232.76.173] (port=50535 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MGeHz-0004Yn-0t for qemu-devel@nongnu.org; Tue, 16 Jun 2009 15:25:47 -0400 Received: from mx2.redhat.com ([66.187.237.31]:35705) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MGeHy-0001kB-Gu for qemu-devel@nongnu.org; Tue, 16 Jun 2009 15:25:46 -0400 Date: Tue, 16 Jun 2009 22:23:39 +0300 From: Gleb Natapov Subject: Re: [Qemu-devel] Register uhci_reset() callback. Message-ID: <20090616192339.GJ782@redhat.com> References: <20090611084808.GA19508@redhat.com> <200906161754.59643.paul@codesourcery.com> <200906161900.11811.paul@codesourcery.com> <20090616185218.GK11893@shareable.org> <20090616190529.GO11893@shareable.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Paul Brook , qemu-devel@nongnu.org, Avi Kivity On Tue, Jun 16, 2009 at 10:10:59PM +0300, Blue Swirl wrote: > > That's why real hardware has a nice long reset pulse, during which > > every input change is ignored until the reset pulse is removed. > > qemu_irq does not have state. It's different from real HW IRQ, so QEMU > devices don't need to do anything. I also had this confused earlier. > Yes, qemu_irq does not have state, but nonetheless the sate exists. It is maintained inside piix3 (this is just implementation detail that may or may not go away). But who, if not device itself, should know better what IRQ level should be in any given time? You can literally call qemu_irq() after each line of device emulation code and it will be OK, slow may be, but correct. The more you call qemu_irq() the more closely you emulate real HW level interrupt. -- Gleb.