* [Qemu-devel] [PATCH] sparc64: use pci_mem_base
@ 2009-06-16 23:00 Igor Kovalenko
2009-06-16 23:13 ` Paul Brook
0 siblings, 1 reply; 5+ messages in thread
From: Igor Kovalenko @ 2009-06-16 23:00 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1: Type: text/plain, Size: 951 bytes --]
ultrasparc II maps pci memory space at offset 0x1ff00000000
(or another large offset, depending on cpu type) so we need to
provide offset for e.g. vga to map it's video memory there.
Currently video memory shows up in the area used by sparc silo
boot loader to store kernel and initrd, which leads to corrupted
memory and funny video patterns around kernel panic traces.
Fortunately there exists global pci_mem_base variable which
is used by pci_to_cpu_addr() but it seems to be only called
while clearing pci memory mapping.
This patch adds missing translation call to pci_update_mappings()
and initializes pci_mem_base to 0 by default. Then sun4u sets
required pci memory space offset using pci_mem_base.
PCIMapIORegionFunc parameter addr type changed to
target_phys_addr_t and all uses changed accordingly, including
printf parameter in e1000.c
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
--
Kind regards,
Igor V. Kovalenko
[-- Attachment #2: sparc64-pci-space.patch --]
[-- Type: application/octet-stream, Size: 15110 bytes --]
Index: qemu-trunk/hw/sun4u.c
===================================================================
--- qemu-trunk.orig/hw/sun4u.c
+++ qemu-trunk/hw/sun4u.c
@@ -288,7 +288,7 @@ static const int parallel_irq[MAX_PARALL
static fdctrl_t *floppy_controller;
static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
switch (region_num) {
@@ -453,6 +453,7 @@ static void sun4uv_init(ram_addr_t RAM_s
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,
&pci_bus3);
isa_mem_base = VGA_BASE;
+ pci_mem_base = APB_MEM_BASE;
pci_vga_init(pci_bus, 0, 0);
// XXX Should be pci_bus3
Index: qemu-trunk/hw/pci.c
===================================================================
--- qemu-trunk.orig/hw/pci.c
+++ qemu-trunk/hw/pci.c
@@ -51,7 +51,7 @@ struct PCIBus {
static void pci_update_mappings(PCIDevice *d);
static void pci_set_irq(void *opaque, int irq_num, int level);
-target_phys_addr_t pci_mem_base;
+target_phys_addr_t pci_mem_base = 0;
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
static PCIBus *first_bus;
@@ -424,7 +424,7 @@ static void pci_update_mappings(PCIDevic
}
r->addr = new_addr;
if (r->addr != -1) {
- r->map_func(d, i, r->addr, r->size, r->type);
+ r->map_func(d, i, pci_to_cpu_addr(r->addr), r->size, r->type);
}
}
}
Index: qemu-trunk/hw/pci.h
===================================================================
--- qemu-trunk.orig/hw/pci.h
+++ qemu-trunk/hw/pci.h
@@ -75,7 +75,7 @@ typedef void PCIConfigWriteFunc(PCIDevic
typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
uint32_t address, int len);
typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type);
+ target_phys_addr_t addr, uint32_t size, int type);
typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
#define PCI_ADDRESS_SPACE_MEM 0x00
Index: qemu-trunk/hw/virtio-pci.c
===================================================================
--- qemu-trunk.orig/hw/virtio-pci.c
+++ qemu-trunk/hw/virtio-pci.c
@@ -210,7 +210,7 @@ static void virtio_pci_config_writel(voi
}
static void virtio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev);
VirtIODevice *vdev = proxy->vdev;
Index: qemu-trunk/hw/ac97.c
===================================================================
--- qemu-trunk.orig/hw/ac97.c
+++ qemu-trunk/hw/ac97.c
@@ -1267,7 +1267,7 @@ static int ac97_load (QEMUFile *f, void
}
static void ac97_map (PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIAC97LinkState *d = (PCIAC97LinkState *) pci_dev;
AC97LinkState *s = &d->ac97;
Index: qemu-trunk/hw/cirrus_vga.c
===================================================================
--- qemu-trunk.orig/hw/cirrus_vga.c
+++ qemu-trunk/hw/cirrus_vga.c
@@ -3260,7 +3260,7 @@ void isa_cirrus_vga_init(void)
***************************************/
static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
@@ -3281,7 +3281,7 @@ static void cirrus_pci_lfb_map(PCIDevice
}
static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
Index: qemu-trunk/hw/e1000.c
===================================================================
--- qemu-trunk.orig/hw/e1000.c
+++ qemu-trunk/hw/e1000.c
@@ -143,10 +143,10 @@ static const char phy_regcap[0x20] = {
};
static void
-ioport_map(PCIDevice *pci_dev, int region_num, uint32_t addr,
+ioport_map(PCIDevice *pci_dev, int region_num, target_phys_addr_t addr,
uint32_t size, int type)
{
- DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
+ DBGOUT(IO, "e1000_ioport_map addr=0x" TARGET_FMT_plx " size=0x%08x\n", addr, size);
}
static void
@@ -1028,7 +1028,7 @@ static CPUReadMemoryFunc *e1000_mmio_rea
static void
e1000_mmio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
E1000State *d = (E1000State *)pci_dev;
int i;
@@ -1038,7 +1038,7 @@ e1000_mmio_map(PCIDevice *pci_dev, int r
};
- DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
+ DBGOUT(MMIO, "e1000_mmio_map addr=0x" TARGET_FMT_plx " 0x%08x\n", addr, size);
cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
qemu_register_coalesced_mmio(addr, excluded_regs[0]);
Index: qemu-trunk/hw/eepro100.c
===================================================================
--- qemu-trunk.orig/hw/eepro100.c
+++ qemu-trunk/hw/eepro100.c
@@ -1345,7 +1345,7 @@ typedef struct PCIEEPRO100State {
} PCIEEPRO100State;
static void pci_map(PCIDevice * pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev;
EEPRO100State *s = &d->eepro100;
@@ -1419,7 +1419,7 @@ static CPUReadMemoryFunc *pci_mmio_read[
};
static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev;
Index: qemu-trunk/hw/es1370.c
===================================================================
--- qemu-trunk.orig/hw/es1370.c
+++ qemu-trunk/hw/es1370.c
@@ -913,7 +913,7 @@ static void es1370_adc_callback (void *o
}
static void es1370_map (PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIES1370State *d = (PCIES1370State *) pci_dev;
ES1370State *s = &d->es1370;
Index: qemu-trunk/hw/ide.c
===================================================================
--- qemu-trunk.orig/hw/ide.c
+++ qemu-trunk/hw/ide.c
@@ -2911,7 +2911,7 @@ void isa_ide_init(int iobase, int iobase
static void cmd646_update_irq(PCIIDEState *d);
static void ide_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIIDEState *d = (PCIIDEState *)pci_dev;
IDEState *ide_state;
@@ -3142,7 +3142,7 @@ static void bmdma_addr_writel(void *opaq
}
static void bmdma_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIIDEState *d = (PCIIDEState *)pci_dev;
int i;
Index: qemu-trunk/hw/lsi53c895a.c
===================================================================
--- qemu-trunk.orig/hw/lsi53c895a.c
+++ qemu-trunk/hw/lsi53c895a.c
@@ -1907,7 +1907,7 @@ static void lsi_io_writel(void *opaque,
}
static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
LSIState *s = (LSIState *)pci_dev;
@@ -1922,7 +1922,7 @@ static void lsi_io_mapfunc(PCIDevice *pc
}
static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
LSIState *s = (LSIState *)pci_dev;
@@ -1932,7 +1932,7 @@ static void lsi_ram_mapfunc(PCIDevice *p
}
static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
LSIState *s = (LSIState *)pci_dev;
Index: qemu-trunk/hw/macio.c
===================================================================
--- qemu-trunk.orig/hw/macio.c
+++ qemu-trunk/hw/macio.c
@@ -40,7 +40,7 @@ struct macio_state_t {
};
static void macio_map (PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
macio_state_t *macio_state;
int i;
Index: qemu-trunk/hw/ne2000.c
===================================================================
--- qemu-trunk.orig/hw/ne2000.c
+++ qemu-trunk/hw/ne2000.c
@@ -777,7 +777,7 @@ typedef struct PCINE2000State {
} PCINE2000State;
static void ne2000_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCINE2000State *d = (PCINE2000State *)pci_dev;
NE2000State *s = &d->ne2000;
Index: qemu-trunk/hw/openpic.c
===================================================================
--- qemu-trunk.orig/hw/openpic.c
+++ qemu-trunk/hw/openpic.c
@@ -1026,7 +1026,7 @@ static CPUReadMemoryFunc *openpic_read[]
};
static void openpic_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
openpic_t *opp;
Index: qemu-trunk/hw/pcnet.c
===================================================================
--- qemu-trunk.orig/hw/pcnet.c
+++ qemu-trunk/hw/pcnet.c
@@ -1762,7 +1762,7 @@ static uint32_t pcnet_ioport_readl(void
}
static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCNetState *d = &((PCIPCNetState *)pci_dev)->state;
@@ -1976,7 +1976,7 @@ static CPUReadMemoryFunc *pcnet_mmio_rea
};
static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIPCNetState *d = (PCIPCNetState *)pci_dev;
Index: qemu-trunk/hw/rtl8139.c
===================================================================
--- qemu-trunk.orig/hw/rtl8139.c
+++ qemu-trunk/hw/rtl8139.c
@@ -3331,7 +3331,7 @@ typedef struct PCIRTL8139State {
} PCIRTL8139State;
static void rtl8139_mmio_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
RTL8139State *s = &d->rtl8139;
@@ -3340,7 +3340,7 @@ static void rtl8139_mmio_map(PCIDevice *
}
static void rtl8139_ioport_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIRTL8139State *d = (PCIRTL8139State *)pci_dev;
RTL8139State *s = &d->rtl8139;
Index: qemu-trunk/hw/usb-ohci.c
===================================================================
--- qemu-trunk.orig/hw/usb-ohci.c
+++ qemu-trunk/hw/usb-ohci.c
@@ -1705,7 +1705,7 @@ typedef struct {
} OHCIPCIState;
static void ohci_mapfunc(PCIDevice *pci_dev, int i,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
OHCIPCIState *ohci = (OHCIPCIState *)pci_dev;
cpu_register_physical_memory(addr, size, ohci->state.mem);
Index: qemu-trunk/hw/usb-uhci.c
===================================================================
--- qemu-trunk.orig/hw/usb-uhci.c
+++ qemu-trunk/hw/usb-uhci.c
@@ -1057,7 +1057,7 @@ static void uhci_frame_timer(void *opaqu
}
static void uhci_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
UHCIState *s = (UHCIState *)pci_dev;
Index: qemu-trunk/hw/vga.c
===================================================================
--- qemu-trunk.orig/hw/vga.c
+++ qemu-trunk/hw/vga.c
@@ -2236,7 +2236,7 @@ void vga_dirty_log_start(VGAState *s)
}
static void vga_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
PCIVGAState *d = (PCIVGAState *)pci_dev;
VGAState *s = &d->vga_state;
Index: qemu-trunk/hw/vmware_vga.c
===================================================================
--- qemu-trunk.orig/hw/vmware_vga.c
+++ qemu-trunk/hw/vmware_vga.c
@@ -1173,7 +1173,7 @@ static int pci_vmsvga_load(QEMUFile *f,
}
static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
struct vmsvga_state_s *s = &d->chip;
@@ -1193,7 +1193,7 @@ static void pci_vmsvga_map_ioport(PCIDev
}
static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
struct vmsvga_state_s *s = &d->chip;
Index: qemu-trunk/hw/wdt_i6300esb.c
===================================================================
--- qemu-trunk.orig/hw/wdt_i6300esb.c
+++ qemu-trunk/hw/wdt_i6300esb.c
@@ -351,7 +351,7 @@ static void i6300esb_mem_writel(void *vp
}
static void i6300esb_map(PCIDevice *dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ target_phys_addr_t addr, uint32_t size, int type)
{
static CPUReadMemoryFunc *mem_read[3] = {
i6300esb_mem_readb,
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [Qemu-devel] [PATCH] sparc64: use pci_mem_base
2009-06-16 23:00 [Qemu-devel] [PATCH] sparc64: use pci_mem_base Igor Kovalenko
@ 2009-06-16 23:13 ` Paul Brook
2009-06-16 23:24 ` Igor Kovalenko
0 siblings, 1 reply; 5+ messages in thread
From: Paul Brook @ 2009-06-16 23:13 UTC (permalink / raw)
To: qemu-devel
> Fortunately there exists global pci_mem_base variable which
> is used by pci_to_cpu_addr() but it seems to be only called
> while clearing pci memory mapping.
I think this is the wrong way to fix this. Better would be for the map
functions to go away altogether.
Paul
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH] sparc64: use pci_mem_base
2009-06-16 23:13 ` Paul Brook
@ 2009-06-16 23:24 ` Igor Kovalenko
2009-06-17 0:06 ` Paul Brook
0 siblings, 1 reply; 5+ messages in thread
From: Igor Kovalenko @ 2009-06-16 23:24 UTC (permalink / raw)
To: Paul Brook; +Cc: qemu-devel
On Wed, Jun 17, 2009 at 3:13 AM, Paul Brook<paul@codesourcery.com> wrote:
>> Fortunately there exists global pci_mem_base variable which
>> is used by pci_to_cpu_addr() but it seems to be only called
>> while clearing pci memory mapping.
>
> I think this is the wrong way to fix this. Better would be for the map
> functions to go away altogether.
Like pci bus would handle that memory address mapping between
devices and cpu?
--
Kind regards,
Igor V. Kovalenko
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH] sparc64: use pci_mem_base
2009-06-16 23:24 ` Igor Kovalenko
@ 2009-06-17 0:06 ` Paul Brook
2009-06-17 7:13 ` Avi Kivity
0 siblings, 1 reply; 5+ messages in thread
From: Paul Brook @ 2009-06-17 0:06 UTC (permalink / raw)
To: qemu-devel
On Wednesday 17 June 2009, Igor Kovalenko wrote:
> On Wed, Jun 17, 2009 at 3:13 AM, Paul Brook<paul@codesourcery.com> wrote:
> >> Fortunately there exists global pci_mem_base variable which
> >> is used by pci_to_cpu_addr() but it seems to be only called
> >> while clearing pci memory mapping.
> >
> > I think this is the wrong way to fix this. Better would be for the map
> > functions to go away altogether.
>
> Like pci bus would handle that memory address mapping between
> devices and cpu?
Yes. In fact individual devices generally shouldn't need to know about the
mappings at all. They should just provide a handler for accesses via a
particular BAR.
Paul
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [PATCH] sparc64: use pci_mem_base
2009-06-17 0:06 ` Paul Brook
@ 2009-06-17 7:13 ` Avi Kivity
0 siblings, 0 replies; 5+ messages in thread
From: Avi Kivity @ 2009-06-17 7:13 UTC (permalink / raw)
To: Paul Brook; +Cc: qemu-devel
On 06/17/2009 03:06 AM, Paul Brook wrote:
>> Like pci bus would handle that memory address mapping between
>> devices and cpu?
>>
>
> Yes. In fact individual devices generally shouldn't need to know about the
> mappings at all. They should just provide a handler for accesses via a
> particular BAR.
>
I have a patch series which may help with this, I just need to rebase it.
--
Do not meddle in the internals of kernels, for they are subtle and quick to panic.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2009-06-17 7:15 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2009-06-16 23:00 [Qemu-devel] [PATCH] sparc64: use pci_mem_base Igor Kovalenko
2009-06-16 23:13 ` Paul Brook
2009-06-16 23:24 ` Igor Kovalenko
2009-06-17 0:06 ` Paul Brook
2009-06-17 7:13 ` Avi Kivity
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