From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MHAiJ-0003Zx-Ae for qemu-devel@nongnu.org; Thu, 18 Jun 2009 02:03:07 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MHAiD-0003YQ-Aq for qemu-devel@nongnu.org; Thu, 18 Jun 2009 02:03:05 -0400 Received: from [199.232.76.173] (port=41574 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MHAiC-0003YN-QN for qemu-devel@nongnu.org; Thu, 18 Jun 2009 02:03:00 -0400 Received: from mx2.redhat.com ([66.187.237.31]:44053) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MHAiC-0006qR-26 for qemu-devel@nongnu.org; Thu, 18 Jun 2009 02:03:00 -0400 Date: Thu, 18 Jun 2009 09:02:56 +0300 From: Gleb Natapov Subject: Re: [Qemu-devel] [PATCH 2/3] Call piix3_reset() on system reset. Message-ID: <20090618060255.GA20289@redhat.com> References: <1245256322-30990-1-git-send-email-gleb@redhat.com> <1245256322-30990-2-git-send-email-gleb@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org On Wed, Jun 17, 2009 at 08:10:23PM +0300, Blue Swirl wrote: > On 6/17/09, Gleb Natapov wrote: > > Also zero pci_irq_levels on reset to avoid stuck irq after reset. > > > > Signed-off-by: Gleb Natapov > > Signed-off-by: Yaniv Kamay > > Thanks, applied. Thanks, but without 1/3 reset is still buggy. Look at hw/pci.c:pci_set_irq() If pci_dev->irq_state[irq_num] == 1 at reset time it will stay 1 after reset too. When device will try to race IRQ line after reset it will fail to do so. And if bus->irq_count[] is not zeroed you have another set of problems. If you don't like that pci_bus_reset() reset per device state (why?) it is possible to create pci_device_reset(), but then we will have to fix 25 devices to call it. Complication for no good reason. IMHO pci_device_save/load should be handled in hw/pci.c too. What are the disadvantages? -- Gleb.