From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MKSmf-00072u-9C for qemu-devel@nongnu.org; Sat, 27 Jun 2009 03:57:13 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MKSma-0006wD-C1 for qemu-devel@nongnu.org; Sat, 27 Jun 2009 03:57:12 -0400 Received: from [199.232.76.173] (port=52082 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MKSma-0006vq-4Q for qemu-devel@nongnu.org; Sat, 27 Jun 2009 03:57:08 -0400 Received: from fmmailgate01.web.de ([217.72.192.221]:44244) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MKSmZ-0007QK-A8 for qemu-devel@nongnu.org; Sat, 27 Jun 2009 03:57:07 -0400 Resent-To: Anthony Liguori Resent-Message-Id: <4A45D0D1.3080103@web.de> From: Jan Kiszka Date: Sat, 27 Jun 2009 09:53:51 +0200 Message-ID: <20090627075351.13376.20106.stgit@mchn012c.ww002.siemens.net> In-Reply-To: <20090627075350.13376.17936.stgit@mchn012c.ww002.siemens.net> References: <20090627075350.13376.17936.stgit@mchn012c.ww002.siemens.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Sender: jan.kiszka@web.de Subject: [Qemu-devel] [PATCH 4/4] gdbstub: x86: Switch 64/32 bit registers dynamically List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org, Paul Brook Commit 56aebc891674cd2d07b3f64183415697be200084 changed gdbstub in way that debugging 32 or 16-bit guest code is no longer possible with qemu for x86_64 guest CPUs. Since that commit, qemu only provides registers sets for 64-bit, forcing current and foreseeable gdb to also switch its architecture to 64-bit. And this breaks if the inferior is 32 or 16 bit. No question, this is a gdb issue. But, as it was confirmed in several discusssions with gdb people, it is a non-trivial thing to fix. So until qemu finds a gdb version attach with a rework x86 support, we have to work around it by switching the register layout as the guest switches its execution mode between 16/32 and 64 bit. Signed-off-by: Jan Kiszka --- gdbstub.c | 53 ++++++++++++++++++++++++++++++++++++++++------------- target-i386/cpu.h | 7 +++++-- 2 files changed, 45 insertions(+), 15 deletions(-) diff --git a/gdbstub.c b/gdbstub.c index 24297ba..618edc8 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -506,8 +506,9 @@ static const int gpr_map[16] = { 8, 9, 10, 11, 12, 13, 14, 15 }; #else -static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7}; +#define gpr_map gpr_map32 #endif +static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25) @@ -521,7 +522,10 @@ static const int gpr_map[8] = {0, 1, 2, 3, 4, 5, 6, 7}; static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) { if (n < CPU_NB_REGS) { - GET_REGL(env->regs[gpr_map[n]]); + if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)) + GET_REGL(env->regs[gpr_map[n]]); + else if (n < CPU_NB_REGS32) + GET_REG32(env->regs[gpr_map32[n]]); } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { #ifdef USE_X86LDOUBLE /* FIXME: byteswap float values - after fixing fpregs layout. */ @@ -532,12 +536,19 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) return 10; } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { n -= IDX_XMM_REGS; - stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0)); - stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1)); - return 16; + if (n < CPU_NB_REGS32 + || (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK))) { + stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0)); + stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1)); + return 16; + } } else { switch (n) { - case IDX_IP_REG: GET_REGL(env->eip); + case IDX_IP_REG: + if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)) + GET_REG64(env->eip); + else + GET_REG32(env->eip); case IDX_FLAGS_REG: GET_REG32(env->eflags); case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector); @@ -593,8 +604,15 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) uint32_t tmp; if (n < CPU_NB_REGS) { - env->regs[gpr_map[n]] = ldtul_p(mem_buf); - return sizeof(target_ulong); + if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)) { + env->regs[gpr_map[n]] = ldtul_p(mem_buf); + return sizeof(target_ulong); + } else if (n < CPU_NB_REGS32) { + n = gpr_map32[n]; + env->regs[n] &= ~0xffffffffUL; + env->regs[n] |= (uint32_t)ldl_p(mem_buf); + return 4; + } } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) { #ifdef USE_X86LDOUBLE /* FIXME: byteswap float values - after fixing fpregs layout. */ @@ -603,14 +621,23 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) return 10; } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) { n -= IDX_XMM_REGS; - env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf); - env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8); - return 16; + if (n < CPU_NB_REGS32 + || (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK))) { + env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf); + env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8); + return 16; + } } else { switch (n) { case IDX_IP_REG: - env->eip = ldtul_p(mem_buf); - return sizeof(target_ulong); + if (TARGET_LONG_BITS == 64 && (env->hflags & HF_CS64_MASK)) { + env->eip = ldq_p(mem_buf); + return 8; + } else { + env->eip &= ~0xffffffffUL; + env->eip |= (uint32_t)ldl_p(mem_buf); + return 4; + } case IDX_FLAGS_REG: env->eflags = ldl_p(mem_buf); return 4; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index aa35987..c01ebea 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -538,10 +538,13 @@ typedef union { #endif #define MMX_Q(n) q +#define CPU_NB_REGS64 16 +#define CPU_NB_REGS32 8 + #ifdef TARGET_X86_64 -#define CPU_NB_REGS 16 +#define CPU_NB_REGS CPU_NB_REGS64 #else -#define CPU_NB_REGS 8 +#define CPU_NB_REGS CPU_NB_REGS32 #endif #define NB_MMU_MODES 2