From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MLOnS-0007uL-76 for qemu-devel@nongnu.org; Mon, 29 Jun 2009 17:53:54 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MLOnN-0007sf-IJ for qemu-devel@nongnu.org; Mon, 29 Jun 2009 17:53:53 -0400 Received: from [199.232.76.173] (port=44575 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MLOnN-0007sc-FT for qemu-devel@nongnu.org; Mon, 29 Jun 2009 17:53:49 -0400 Received: from mail2.shareable.org ([80.68.89.115]:54328) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MLOnM-0005wC-Vg for qemu-devel@nongnu.org; Mon, 29 Jun 2009 17:53:49 -0400 Date: Mon, 29 Jun 2009 22:53:45 +0100 From: Jamie Lokier Subject: Re: [Qemu-devel] [PATCH] Implement PC port80 debug register. Message-ID: <20090629215345.GA7761@shareable.org> References: <1246262725-23825-1-git-send-email-jljusten@gmail.com> <4A48C5F5.6030402@codemonkey.ws> <4A48CE67.9070705@redhat.com> <2a50f7880906290826t4128b11dyc68a36fd01e8208c@mail.gmail.com> <4A48DF8B.7050606@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A48DF8B.7050606@redhat.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Jordan Justen , qemu-devel@nongnu.org Avi Kivity wrote: > On 06/29/2009 06:26 PM, Jordan Justen wrote: > >Avi, > > > >Well, I am not sure if this it globally the case for PC motherboards, > >but in my experience, it has been read/write. > > It's just some random memory that might not actually be grounded in reality. It is not memory, and it's not even an I/O port. On many PCs, at least historically, it resolves to an ISA bus cycle which no device responds to, and therefore takes about 1 microsecond with side effects which help some ISA devices (on other I/O ports) to work. Including 2MHz ISA devices on an 8MHz ISA bus... so it has to be a port which isn't on the device it's helping :-) (Good) modern chipsets tend to not need the delay or side effects, but they emulate the delay anyway. When an ISA BIOS POST debugging card is plugged in, or if there's one on the motherboard, then it catches the writes and displays them as hex on LEDs. That changes the timing and can in principle break some things... Some Linux distros write to port 0xed instead of 0x80 now, because some HP/Compaq laptops break when writing to port 0x80 after ACPI is enabled. (Silly BIOS bugs). But 0xed breaks some old ISA systems, because it doesn't have quite the same bus side effects. Enjoy. > >At least for a system such as qemu, it make it difficult to use the > >port80 checkpoint of software without being able to read the last > >value written. > > Why would software ever need to read it? You want a monitor command so > the user can read it. I don't recall ever seeing a read of port 80 (I > don't have any objections to that though). Because most ISA PCs don't have anything there, reading won't return anything interesting. It won't return the value written. But maybe with a BIOS POST debugging card, and/or maybe with some chipsets which are emulating the port... I don't know. -- Jamie