From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MLnde-000096-K1 for qemu-devel@nongnu.org; Tue, 30 Jun 2009 20:25:26 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MLnda-00007U-5L for qemu-devel@nongnu.org; Tue, 30 Jun 2009 20:25:26 -0400 Received: from [199.232.76.173] (port=37871 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MLndZ-00007R-Ug for qemu-devel@nongnu.org; Tue, 30 Jun 2009 20:25:21 -0400 Received: from mx20.gnu.org ([199.232.41.8]:45027) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MLndZ-0007Q7-KT for qemu-devel@nongnu.org; Tue, 30 Jun 2009 20:25:21 -0400 Received: from mail.codesourcery.com ([65.74.133.4]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MLndY-0002ju-Fj for qemu-devel@nongnu.org; Tue, 30 Jun 2009 20:25:20 -0400 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH 4/8] qdev/core: bus list Date: Wed, 1 Jul 2009 01:25:14 +0100 References: <1246353962-32308-1-git-send-email-kraxel@redhat.com> <4A4A6C48.3060101@codemonkey.ws> <4A4A731D.5020306@redhat.com> In-Reply-To: <4A4A731D.5020306@redhat.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200907010125.16181.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Gerd Hoffmann , Markus Armbruster On Tuesday 30 June 2009, Gerd Hoffmann wrote: > On 06/30/09 21:49, Anthony Liguori wrote: > > I think it's a perfectly valid suggestion that we should identify buses > > based on the their location in the tree to users verses a number > > generated based on some hashing algorithm. > > > > A tree location has meaning to a user. A random integer doesn't. > > Well. Depends on the bus I think. About PCI devices the usual user > probably thinks in terms of "$bus:$slot.$function", which includes a bus > number. > > Speaking of PCI: the PCI bus number (aka PCIBus->bus_num) has nothing to > do with the more or less random bus number introduced by the (now > dropped) patch (aka PCIBus->qdev.busnr). Which indicates that it is > probably less confusing to have the bus implementation handle the > enumeration of busses. If it makes sense for the bus in question of > course. sysbus probably doesn't care ;) PCI bus numbers should be determined by the guest, and are not fixed values. The only reason we get away with it now is because most guests will honor a pre-existing bridge device configuration. A guest firmware could choose to enumerate the PCI busses in a different order. Paul