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Date: Mon, 6 Jul 2009 08:28:55 -0700
From: Nathan Froyd <froydnj@codesourcery.com>
Subject: Re: [Qemu-devel] [PATCH 0/7] target-ppc/linux-user: NPTL support
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	<Pine.LNX.4.64.0906060302040.27655@linmac.oyster.ru>
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To: malc <av1474@comtv.ru>
Cc: qemu-devel@nongnu.org

On Sat, Jun 06, 2009 at 03:04:38AM +0400, malc wrote:
> On Thu, 4 Jun 2009, Nathan Froyd wrote:
> > The main complication comes from implementing atomic instructions
> > properly.  We chose to implement a simplistic model:
> > 
> > - reserved loads record the value loaded;
> > 
> > - conditional stores check that the memory at the effective address
> >   contains the value loaded by the previous reserved load, in addition
> >   to all other checks.  if so, the store succeeds; otherwise, it fails.
> 
> I think this will break code that relies on the fact that ll/sc is not
> affected by the ABA problem.
>
> > It is possible to implement something more sophisticated using mprotect:

The simpler scheme is slightly faster than mprotect, but not
astonishingly so.  In practice, it works out OK, even if it doesn't
adhere to a particular interpretation of the chip docs.

I'm ambivalent about which scheme goes in: I just would like to see
something go in so atomic instructions/user-mode emulation threading can
be properly supported on PPC (and other architectures to follow, I'm
sure...).

-Nathan