From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MaUnf-0007mJ-Cx for qemu-devel@nongnu.org; Mon, 10 Aug 2009 09:20:31 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MaUna-0007gk-SW for qemu-devel@nongnu.org; Mon, 10 Aug 2009 09:20:31 -0400 Received: from [199.232.76.173] (port=50736 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MaUna-0007gV-DI for qemu-devel@nongnu.org; Mon, 10 Aug 2009 09:20:26 -0400 Received: from mail.gmx.net ([213.165.64.20]:37680) by monty-python.gnu.org with smtp (Exim 4.60) (envelope-from ) id 1MaUnZ-0001A5-Kc for qemu-devel@nongnu.org; Mon, 10 Aug 2009 09:20:26 -0400 Date: Mon, 10 Aug 2009 15:20:47 +0200 From: Olaf Dabrunz Subject: Re: [Qemu-devel] [PATCH 1/2] Route PC irqs to ISA bus instead of i8259 directly Message-ID: <20090810132047.GC14714@santana.dyndns.org> References: <1249836296-13288-1-git-send-email-avi@redhat.com> <1249836296-13288-2-git-send-email-avi@redhat.com> <2202BB40-5CA5-462B-8A5A-A9657B370B6D@suse.de> <4A7FEC23.1050708@redhat.com> <4A7FEDF3.1060608@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A7FEDF3.1060608@redhat.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Olaf Dabrunz , Alexander Graf , Stefan Assmann , "qemu-devel@nongnu.org" On 10-Aug-09, Avi Kivity wrote: > On 08/10/2009 12:45 PM, Stefan Assmann wrote: >> Does qemu support multiple IO-APICs? I guess not so no need for boot >> interrupts. (If yes then there would be the question how close you >> really want to be to existing hardware.) > > > Not at present. We've considered adding IOAPICs to reduce interrupt > sharing, but MSI solves the problem much more neatly. Yes, all modern operating systems that come to my mind support MSIs, so as long as you do not want to run some old system, this is ok. I also guess that you do not try to emulate one of the chipsets that has a broken MSI implementation. -- Olaf Dabrunz (Olaf.Dabrunz gmx.net)