From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Maygj-0003Tj-95 for qemu-devel@nongnu.org; Tue, 11 Aug 2009 17:15:21 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Mayge-0003RV-6X for qemu-devel@nongnu.org; Tue, 11 Aug 2009 17:15:20 -0400 Received: from [199.232.76.173] (port=33565 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Maygd-0003RM-VM for qemu-devel@nongnu.org; Tue, 11 Aug 2009 17:15:16 -0400 Received: from mail.gmx.net ([213.165.64.20]:50993) by monty-python.gnu.org with smtp (Exim 4.60) (envelope-from ) id 1Maygd-0001sa-Dp for qemu-devel@nongnu.org; Tue, 11 Aug 2009 17:15:15 -0400 Date: Tue, 11 Aug 2009 23:15:09 +0200 From: Reimar =?iso-8859-1?Q?D=F6ffinger?= Message-ID: <20090811211509.GD10500@1und1.de> References: <4A81D3F1.1040300@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4A81D3F1.1040300@codemonkey.ws> Subject: [Qemu-devel] [PATCH 3/5] Add support for receiving via receive buffers. While the Intel documentation claims this is unsupported, the OS X drivers use it, causing an assertion failure since rx buffer size is 0. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org This adds support for some kind of receive buffers "flexible mode". The Intel documentation as I read it claims that no such mode exist for receive, but the fact that those (working with real hardware I expect) drivers use it contradicts that... This _definitely_ is necessary to support these AppleIntel8255x drivers. Signed-off-by: Reimar Döffinger --- hw/eepro100.c | 27 ++++++++++++++++++++++++--- 1 files changed, 24 insertions(+), 3 deletions(-) diff --git a/hw/eepro100.c b/hw/eepro100.c index f619d36..5620bc7 100644 --- a/hw/eepro100.c +++ b/hw/eepro100.c @@ -153,6 +153,14 @@ typedef struct { char packet[MAX_ETH_FRAME_SIZE + 4]; } eepro100_rx_t; +/* Receive buffer descriptor. */ +typedef struct { + uint32_t count; + uint32_t link; + uint32_t buffer; + uint32_t size; +} eepro100_rbd_t; + typedef struct { uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions, tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions, @@ -218,6 +226,7 @@ typedef struct { /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */ uint32_t ru_base; /* RU base address */ uint32_t ru_offset; /* RU address offset */ + uint32_t rbd_addr; uint32_t statsaddr; /* pointer to eepro100_stats_t */ eepro100_stats_t statistics; /* statistical counters */ #if 0 @@ -843,6 +852,7 @@ static void eepro100_ru_command(EEPRO100State * s, uint8_t val) } set_ru_state(s, ru_ready); s->ru_offset = s->pointer; + s->rbd_addr = 0; logout("val=0x%02x (rx start)\n", val); break; case RX_RESUME: @@ -1512,7 +1522,19 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx, offsetof(eepro100_rx_t, packet)); uint16_t rfd_command = le16_to_cpu(rx.command); - uint16_t rfd_size = le16_to_cpu(rx.size); + uint32_t rfd_size = le16_to_cpu(rx.size); + uint32_t dst_addr = s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, packet); + if (rfd_command & 8) { + // argh! Flexible mode. Intel docs say it is not support but the Mac OS driver uses it anyway. + eepro100_rbd_t rbd; + if (!s->rbd_addr) + s->rbd_addr = le32_to_cpu(rx.rx_buf_addr); + cpu_physical_memory_read(s->rbd_addr, (uint8_t *) & rbd, sizeof(rbd)); + rfd_size = le32_to_cpu(rbd.size); + dst_addr = le32_to_cpu(rbd.buffer); + stl_phys(s->rbd_addr + offsetof(eepro100_rbd_t, count), size | 0x8000); + s->rbd_addr = le32_to_cpu(rbd.link); + } assert(size <= rfd_size); if (size < 64) { rfd_status |= 0x0080; @@ -1528,8 +1550,7 @@ static ssize_t nic_receive(VLANClientState *vc, const uint8_t * buf, size_t size assert(!(s->configuration[18] & 4)); /* TODO: check stripping enable bit. */ //~ assert(!(s->configuration[17] & 1)); - cpu_physical_memory_write(s->ru_base + s->ru_offset + - offsetof(eepro100_rx_t, packet), buf, size); + cpu_physical_memory_write(dst_addr, buf, size); s->statistics.rx_good_frames++; eepro100_fr_interrupt(s); s->ru_offset = le32_to_cpu(rx.link); -- 1.6.4