From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MnFWq-00048p-MU for qemu-devel@nongnu.org; Mon, 14 Sep 2009 13:39:52 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MnFWl-0003z4-Mt for qemu-devel@nongnu.org; Mon, 14 Sep 2009 13:39:51 -0400 Received: from [199.232.76.173] (port=53033 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MnFWl-0003yt-AK for qemu-devel@nongnu.org; Mon, 14 Sep 2009 13:39:47 -0400 Received: from mx1.redhat.com ([209.132.183.28]:18075) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MnFWk-0003Ay-Ew for qemu-devel@nongnu.org; Mon, 14 Sep 2009 13:39:46 -0400 Date: Mon, 14 Sep 2009 20:36:25 +0300 From: "Michael S. Tsirkin" Message-ID: <20090914173625.GA3859@redhat.com> References: <20090914154822.GA3745@redhat.com> <4AAE7A31.9080600@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4AAE7A31.9080600@codemonkey.ws> Subject: [Qemu-devel] Re: pci: is reset incomplete? List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Carsten Otte , Gerd Hoffmann , kvm@vger.kernel.org, Rusty Russell , qemu-devel@nongnu.org, virtualization@lists.linux-foundation.org, Christian Borntraeger , Paul Brook , Avi Kivity On Mon, Sep 14, 2009 at 12:15:29PM -0500, Anthony Liguori wrote: > Michael S. Tsirkin wrote: >> Hi! >> pci bus reset does not seem to clear pci config registers, such as BAR >> registers, or memory space enable, of the attached devices: it only >> clears the interrupt state. >> >> This seems wrong, but easy to fix. >> > > I don't think most pci devices reset their config space in their reset > callbacks. For things like BAR registers, they really must. The PCI spec is quite specific on this point. > I would think that making most of the config space (if not the entire) > qdev properties would make sense. You can then get reset for free and > it's possible for users to tweak things like class codes universally. class codes are read only registers. Your proposal might be correct for some of these. But PCI registers that are reset, change as a result of guest activity, and reset values are typically specified by guest spec. So I don't think we should let users tweak these. > Regards, > > Anthony Liguori > >> Comments? >> >>