From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MsfEW-000280-Op for qemu-devel@nongnu.org; Tue, 29 Sep 2009 12:07:20 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MsfEQ-00020v-IF for qemu-devel@nongnu.org; Tue, 29 Sep 2009 12:07:19 -0400 Received: from [199.232.76.173] (port=35717 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MsfEP-0001zt-TH for qemu-devel@nongnu.org; Tue, 29 Sep 2009 12:07:14 -0400 Received: from mx20.gnu.org ([199.232.41.8]:35364) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1MsfEN-0007vg-53 for qemu-devel@nongnu.org; Tue, 29 Sep 2009 12:07:11 -0400 Received: from mx1.redhat.com ([209.132.183.28]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Msf8U-0006qA-KS for qemu-devel@nongnu.org; Tue, 29 Sep 2009 12:01:07 -0400 Date: Tue, 29 Sep 2009 17:57:57 +0200 From: "Michael S. Tsirkin" Subject: Re: [Qemu-devel] Re: [PATCHv2] qemu: target library, use it in msix Message-ID: <20090929155756.GA13666@redhat.com> References: <4ABF52A5.5080409@redhat.com> <20090927120041.GB24031@redhat.com> <4ABF585D.7000201@redhat.com> <20090927140841.GA24769@redhat.com> <4ABF7359.8050404@redhat.com> <20090927142129.GA24851@redhat.com> <20090927142422.GB24851@redhat.com> <20090929145006.GA3301@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Avi Kivity , qemu-devel@nongnu.org On Tue, Sep 29, 2009 at 06:15:21PM +0300, Blue Swirl wrote: > On Tue, Sep 29, 2009 at 5:50 PM, Michael S. Tsirkin wr= ote: > > On Sun, Sep 27, 2009 at 06:19:05PM +0300, Blue Swirl wrote: > >> On Sun, Sep 27, 2009 at 5:24 PM, Michael S. Tsirkin = wrote: > >> > On Sun, Sep 27, 2009 at 04:21:29PM +0200, Michael S. Tsirkin wrote= : > >> >> On Sun, Sep 27, 2009 at 04:14:49PM +0200, Avi Kivity wrote: > >> >> > On 09/27/2009 04:08 PM, Michael S. Tsirkin wrote: > >> >> >> > >> >> >> > >> >> >>>> In practice, the only user is now msix and it does not. =A0I= t has 0x1000 > >> >> >>>> as a constant parameter. =A0For target_phys_addr_t users if = we ever have > >> >> >>>> them, we'll just add target_phys_page_align. Generally it's = unusual for > >> >> >>>> devices to care about size of target physical page. > >> >> >>>> > >> >> >>>> > >> >> >>> I'd fill better with uint64_t, at least that won't truncate. > >> >> >>> > >> >> >> Doesn't naming it target_page_align32 address this concern? > >> >> >> > >> >> > > >> >> > How can the caller (except in your special case) know if it has= a > >> >> > quantity that will fit in 32 bits? > >> >> > >> >> It's actually not unusual for devices to limit addressing to 32 b= it, whatever > >> >> the bus supports. > >> > > >> > I would say that devices normally have a specific addressing, and = should > >> > not be using target specific types at all. =A0This alignment to ta= rget > >> > page size is actually an unusual thing. > >> > >> Actually, AFAICT MSI-X spec (6.8.2, from the MSI entry in Wikipedia) > >> only requires a QWORD alignment. There is some blurb about 4k > >> alignment, but I think it only describes how software should use the > >> structure. > >> If this is the case, we could drop the whole target page > >> stuff. > > > > The variable MSIX_PAGE_SIZE actually specifies the size of the space > > allocated for MSIX in the memory region. =A0Spec requires locating MS= I-X > > tables in a 4K region separate from any other device register, so fro= m > > that point of view we could just have had > > #define MSIX_PAGE_SIZE 0x1000 >=20 > Can you cite the spec, I only found the QWORD stuff. In spec revision 3.0, see this text: 6.8.2. MSI-X Capability and Table Structures ... If a Base Address register that maps address space for the MSI-X Table o= r MSI-X PBA also maps other usable address space that is not associated with MSI-X struct= ures, locations (e.g., for CSRs) used in the other address space must not share any naturally a= ligned 4-KB address range with one where either MSI-X structure resides. This allows system = software where applicable to use different processor attributes for MSI-X structures an= d the other address > > The main reason I round the space for MSI-X tables up to cpu page siz= e, > > is because I have to call cpu_register_physical_memory on it, which > > requires that size is a multiple of target page size. >=20 > There is no such requirement anymore (since r2868 in 2007), devices > can register regions of arbitrary size and multiple devices can share > a page. Why does the comment on top of cpu_register_physical_memory_offset say otherwise then? Also, this function seems to call kvm_set_phys_mem, which also, apparently, assumes target page alignment. --=20 MST