From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Msjz2-00053M-Uj for qemu-devel@nongnu.org; Tue, 29 Sep 2009 17:11:41 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Msjyy-00050C-Hm for qemu-devel@nongnu.org; Tue, 29 Sep 2009 17:11:40 -0400 Received: from [199.232.76.173] (port=45129 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Msjyy-0004zy-4U for qemu-devel@nongnu.org; Tue, 29 Sep 2009 17:11:36 -0400 Received: from mx1.redhat.com ([209.132.183.28]:3289) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Msjyx-0005je-JY for qemu-devel@nongnu.org; Tue, 29 Sep 2009 17:11:35 -0400 Date: Tue, 29 Sep 2009 23:09:33 +0200 From: "Michael S. Tsirkin" Subject: Re: [Qemu-devel] Re: [PATCHv2] qemu: target library, use it in msix Message-ID: <20090929210933.GA15551@redhat.com> References: <4ABF585D.7000201@redhat.com> <20090927140841.GA24769@redhat.com> <4ABF7359.8050404@redhat.com> <20090927142129.GA24851@redhat.com> <20090927142422.GB24851@redhat.com> <20090929145006.GA3301@redhat.com> <20090929155756.GA13666@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Avi Kivity , qemu-devel@nongnu.org On Tue, Sep 29, 2009 at 10:34:53PM +0300, Blue Swirl wrote: > On Tue, Sep 29, 2009 at 6:57 PM, Michael S. Tsirkin wr= ote: > > On Tue, Sep 29, 2009 at 06:15:21PM +0300, Blue Swirl wrote: > >> On Tue, Sep 29, 2009 at 5:50 PM, Michael S. Tsirkin = wrote: > >> > On Sun, Sep 27, 2009 at 06:19:05PM +0300, Blue Swirl wrote: > >> >> On Sun, Sep 27, 2009 at 5:24 PM, Michael S. Tsirkin wrote: > >> >> > On Sun, Sep 27, 2009 at 04:21:29PM +0200, Michael S. Tsirkin wr= ote: > >> >> >> On Sun, Sep 27, 2009 at 04:14:49PM +0200, Avi Kivity wrote: > >> >> >> > On 09/27/2009 04:08 PM, Michael S. Tsirkin wrote: > >> >> >> >> > >> >> >> >> > >> >> >> >>>> In practice, the only user is now msix and it does not. =A0= It has 0x1000 > >> >> >> >>>> as a constant parameter. =A0For target_phys_addr_t users = if we ever have > >> >> >> >>>> them, we'll just add target_phys_page_align. Generally it= 's unusual for > >> >> >> >>>> devices to care about size of target physical page. > >> >> >> >>>> > >> >> >> >>>> > >> >> >> >>> I'd fill better with uint64_t, at least that won't truncat= e. > >> >> >> >>> > >> >> >> >> Doesn't naming it target_page_align32 address this concern? > >> >> >> >> > >> >> >> > > >> >> >> > How can the caller (except in your special case) know if it = has a > >> >> >> > quantity that will fit in 32 bits? > >> >> >> > >> >> >> It's actually not unusual for devices to limit addressing to 3= 2 bit, whatever > >> >> >> the bus supports. > >> >> > > >> >> > I would say that devices normally have a specific addressing, a= nd should > >> >> > not be using target specific types at all. =A0This alignment to= target > >> >> > page size is actually an unusual thing. > >> >> > >> >> Actually, AFAICT MSI-X spec (6.8.2, from the MSI entry in Wikiped= ia) > >> >> only requires a QWORD alignment. There is some blurb about 4k > >> >> alignment, but I think it only describes how software should use = the > >> >> structure. > >> >> If this is the case, we could drop the whole target page > >> >> stuff. > >> > > >> > The variable MSIX_PAGE_SIZE actually specifies the size of the spa= ce > >> > allocated for MSIX in the memory region. =A0Spec requires locating= MSI-X > >> > tables in a 4K region separate from any other device register, so = from > >> > that point of view we could just have had > >> > #define MSIX_PAGE_SIZE 0x1000 > >> > >> Can you cite the spec, I only found the QWORD stuff. > > > > In spec revision 3.0, see this text: > > > > =A0 =A0 =A0 =A06.8.2. =A0MSI-X Capability and Table Structures > > > > =A0 =A0 =A0 =A0... > > > > =A0 =A0 =A0 =A0If a Base Address register that maps address space for= the MSI-X Table or MSI-X PBA also > > =A0 =A0 =A0 =A0maps other usable address space that is not associated= with MSI-X structures, locations (e.g., > > =A0 =A0 =A0 =A0for CSRs) used in the other address space must not sha= re any naturally aligned 4-KB address > > =A0 =A0 =A0 =A0range with one where either MSI-X structure resides. T= his allows system software where > > =A0 =A0 =A0 =A0applicable to use different processor attributes for M= SI-X structures and the other address >=20 > I think these are instructions for writing system software, not > description on how MSI-X hardware needs the tables laid out. That > means, the tables should use page alignment (in order to support some > CPU attributes), but the hardware only cares that the data is QWORD > aligned. Yes. All I do is make sure tables are page aligned. --=20 MST