Re: [Qemu-devel] [PATCH] x86: Fix exceptions for fxsave/fxrstor

[Aurelien Jarno <aurelien@aurel32.net>]

On Sun, Oct 04, 2009 at 10:43:54PM +0200, Kevin Wolf wrote:
> Am Sonntag, 4. Oktober 2009 12:05 schrieb Aurelien Jarno:
> > On Fri, Oct 02, 2009 at 10:28:57PM +0200, Kevin Wolf wrote:
> > > This patch corrects the following aspects of exception generation in
> > > fxsave/fxrstor:
> > >
> > > * Generate #GP if the operand is not aligned to a 16 byte boundary
> >
> > Agreed.
> >
> > > * Generate #UD if the LOCK prefix is used
> >
> > Agreed.
> >
> > > * For CR0.EM = 1 #NM is generated, not #UD
> >
> > This does not match the Intel manual:
> > | #NM If CR0.TS[bit 3] = 1.
> > |
> > | #UD If CR0.EM[bit 2] = 1.
> > |     If CPUID.01H:EDX.FXSR[bit 24] = 0.
> > |     If the LOCK prefix is used.
> > |
> 
> Hm, you seem to have a different Intel manual. In my copy the CR0.EM part 
> still belongs to #NM. Also, I ran my test code in KVM for comparision and it 
> did generate an #NM (on two different machines, one Intel, one AMD), so I'm 
> quite sure this is right (well, at least not completely wrong).

My copy of the Intel Manual was quite outdated (May 2007). The new
version from September 2009 matches your patch, so I have applied it.
Sorry.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net