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From: Kevin Wolf <mail@kevin-wolf.de>
Subject: Re: [Qemu-devel] [PATCH] x86: Fix exceptions for fxsave/fxrstor
Date: Sun, 4 Oct 2009 22:43:54 +0200
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To: Aurelien Jarno <aurelien@aurel32.net>
Cc: qemu-devel@nongnu.org

Am Sonntag, 4. Oktober 2009 12:05 schrieb Aurelien Jarno:
> On Fri, Oct 02, 2009 at 10:28:57PM +0200, Kevin Wolf wrote:
> > This patch corrects the following aspects of exception generation in
> > fxsave/fxrstor:
> >
> > * Generate #GP if the operand is not aligned to a 16 byte boundary
>
> Agreed.
>
> > * Generate #UD if the LOCK prefix is used
>
> Agreed.
>
> > * For CR0.EM = 1 #NM is generated, not #UD
>
> This does not match the Intel manual:
> | #NM If CR0.TS[bit 3] = 1.
> |
> | #UD If CR0.EM[bit 2] = 1.
> |     If CPUID.01H:EDX.FXSR[bit 24] = 0.
> |     If the LOCK prefix is used.
> |

Hm, you seem to have a different Intel manual. In my copy the CR0.EM part 
still belongs to #NM. Also, I ran my test code in KVM for comparision and it 
did generate an #NM (on two different machines, one Intel, one AMD), so I'm 
quite sure this is right (well, at least not completely wrong).

On the other hand, I just had a look at the AMD documentation and it seems to 
support your version... So while my hardware suggests that #NM is right, I'm 
not going to insist on it. Maybe there is some hardware that actually does 
generate #UD.

If you don't like to commit this part of the fix despite my explanation, just 
let me know and I'll resend the patch without it.

Kevin