From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Muoj3-0000io-KL for qemu-devel@nongnu.org; Mon, 05 Oct 2009 10:39:45 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Muoiz-0000hX-A1 for qemu-devel@nongnu.org; Mon, 05 Oct 2009 10:39:45 -0400 Received: from [199.232.76.173] (port=34040 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Muoiy-0000hP-UJ for qemu-devel@nongnu.org; Mon, 05 Oct 2009 10:39:41 -0400 Received: from mx1.redhat.com ([209.132.183.28]:38180) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Muoiy-0007xV-3t for qemu-devel@nongnu.org; Mon, 05 Oct 2009 10:39:40 -0400 Date: Mon, 5 Oct 2009 16:37:39 +0200 From: "Michael S. Tsirkin" Message-ID: <20091005143739.GG31056@redhat.com> References: <1254737223-16129-1-git-send-email-yamahata@valinux.co.jp> <1254737223-16129-16-git-send-email-yamahata@valinux.co.jp> <20091005143532.GF31056@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20091005143532.GF31056@redhat.com> Subject: [Qemu-devel] Re: [PATCH 15/23] pci_host.h: split non-inline static function in pci_host.h into pci_host.c List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: qemu-devel@nongnu.org On Mon, Oct 05, 2009 at 04:35:33PM +0200, Michael S. Tsirkin wrote: > On Mon, Oct 05, 2009 at 07:06:55PM +0900, Isaku Yamahata wrote: > > Later a structures declared in pci_host.h, PCIHostState, will be used. > > However pci_host.h doesn't allow to include itself easily. This patches > > addresses it. > > > > pci_host.h includes non-inline static functions which are instantiated > > in .c by including pci_host.h. That prevents from including pci_host.h > > to use PCIHostState. > > So split pci_host.h non-inline static functions into pci_host.c. > > Its purpose to include is to instantiate io function for mmio or ioio. > > To avoid including code, we always instantiate both version. > > This is even worse than what we had, file including itself, oh my. > All I suggested was either > - get rid of macro hackery in some sane way And by sane way I mean just let users write their own routines which get proper types, and call pci host. > - make all function static inline > > > Signed-off-by: Isaku Yamahata > > --- > > Makefile.target | 8 ++-- > > hw/apb_pci.c | 21 ++------- > > hw/grackle_pci.c | 24 ++-------- > > hw/gt64xxx.c | 11 +---- > > hw/{pci_host.h => pci_host.c} | 61 +++++++++++++++++++++----- > > hw/pci_host.h | 96 ++++++----------------------------------- > > hw/piix_pci.c | 16 +++---- > > hw/ppc4xx_pci.c | 18 +------- > > hw/ppce500_pci.c | 17 +------ > > hw/prep_pci.c | 14 +++--- > > hw/unin_pci.c | 47 +++++--------------- > > 11 files changed, 105 insertions(+), 228 deletions(-) > > copy hw/{pci_host.h => pci_host.c} (69%) > > > > diff --git a/Makefile.target b/Makefile.target > > index 1f4518c..2da39b7 100644 > > --- a/Makefile.target > > +++ b/Makefile.target > > @@ -186,11 +186,11 @@ obj-i386-y += fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o > > obj-i386-y += cirrus_vga.o apic.o ioapic.o parallel.o acpi.o piix_pci.o > > obj-i386-y += usb-uhci.o vmmouse.o vmport.o vmware_vga.o hpet.o > > obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o > > -obj-i386-y += ne2000-isa.o > > +obj-i386-y += ne2000-isa.o pci_host.o > > > > # shared objects > > obj-ppc-y = ppc.o ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/macio.o > > -obj-ppc-y += vga.o vga-pci.o $(sound-obj-y) dma.o openpic.o > > +obj-ppc-y += vga.o vga-pci.o $(sound-obj-y) dma.o openpic.o pci_host.o > > # PREP target > > obj-ppc-y += pckbd.o serial.o i8259.o i8254.o fdc.o mc146818rtc.o > > obj-ppc-y += prep_pci.o ppc_prep.o ne2000-isa.o > > @@ -217,7 +217,7 @@ obj-mips-y += gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o > > obj-mips-y += piix4.o parallel.o cirrus_vga.o pcspk.o $(sound-obj-y) > > obj-mips-y += mipsnet.o ne2000-isa.o > > obj-mips-y += pflash_cfi01.o > > -obj-mips-y += vmware_vga.o > > +obj-mips-y += vmware_vga.o pci_host.o > > > > obj-microblaze-y = petalogix_s3adsp1800_mmu.o > > > > @@ -244,7 +244,7 @@ obj-cris-y += etraxfs_ser.o > > obj-cris-y += pflash_cfi02.o > > > > ifeq ($(TARGET_ARCH), sparc64) > > -obj-sparc-y = sun4u.o pckbd.o apb_pci.o > > +obj-sparc-y = sun4u.o pckbd.o apb_pci.o pci_host.o > > obj-sparc-y += ide/core.o ide/qdev.o ide/pci.o > > obj-sparc-y += vga.o vga-pci.o > > obj-sparc-y += fdc.o mc146818rtc.o serial.o > > diff --git a/hw/apb_pci.c b/hw/apb_pci.c > > index 381b924..89413b1 100644 > > --- a/hw/apb_pci.c > > +++ b/hw/apb_pci.c > > @@ -28,6 +28,7 @@ > > > > #include "sysbus.h" > > #include "pci.h" > > +#include "pci_host.h" > > > > /* debug APB */ > > //#define DEBUG_APB > > @@ -39,9 +40,6 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) > > #define APB_DPRINTF(fmt, ...) > > #endif > > > > -typedef target_phys_addr_t pci_addr_t; > > -#include "pci_host.h" > > - > > typedef struct APBState { > > SysBusDevice busdev; > > PCIHostState host_state; > > @@ -136,18 +134,6 @@ static CPUReadMemoryFunc * const apb_config_read[] = { > > &apb_config_readl, > > }; > > > > -static CPUWriteMemoryFunc * const pci_apb_write[] = { > > - &pci_host_data_writeb, > > - &pci_host_data_writew, > > - &pci_host_data_writel, > > -}; > > - > > -static CPUReadMemoryFunc * const pci_apb_read[] = { > > - &pci_host_data_readb, > > - &pci_host_data_readw, > > - &pci_host_data_readl, > > -}; > > - > > static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr, > > uint32_t val) > > { > > @@ -284,8 +270,9 @@ static int pci_pbm_init_device(SysBusDevice *dev) > > pci_apb_config_write, s); > > sysbus_init_mmio(dev, 0x10ULL, pci_mem_config); > > /* mem_data */ > > - pci_mem_data = cpu_register_io_memory(pci_apb_read, > > - pci_apb_write, &s->host_state); > > + pci_mem_data = cpu_register_io_memory(pci_host_data_read_mmio, > > + pci_host_data_write_mmio, > > + &s->host_state); > > sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data); > > return 0; > > } > > diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c > > index d878cf6..d29175b 100644 > > --- a/hw/grackle_pci.c > > +++ b/hw/grackle_pci.c > > @@ -26,6 +26,7 @@ > > #include "sysbus.h" > > #include "ppc_mac.h" > > #include "pci.h" > > +#include "pci_host.h" > > > > /* debug Grackle */ > > //#define DEBUG_GRACKLE > > @@ -37,9 +38,6 @@ > > #define GRACKLE_DPRINTF(fmt, ...) > > #endif > > > > -typedef target_phys_addr_t pci_addr_t; > > -#include "pci_host.h" > > - > > typedef struct GrackleState { > > SysBusDevice busdev; > > PCIHostState host_state; > > @@ -84,18 +82,6 @@ static CPUReadMemoryFunc * const pci_grackle_config_read[] = { > > &pci_grackle_config_readl, > > }; > > > > -static CPUWriteMemoryFunc * const pci_grackle_write[] = { > > - &pci_host_data_writeb, > > - &pci_host_data_writew, > > - &pci_host_data_writel, > > -}; > > - > > -static CPUReadMemoryFunc * const pci_grackle_read[] = { > > - &pci_host_data_readb, > > - &pci_host_data_readw, > > - &pci_host_data_readl, > > -}; > > - > > /* Don't know if this matches real hardware, but it agrees with OHW. */ > > static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) > > { > > @@ -163,8 +149,8 @@ static int pci_grackle_init_device(SysBusDevice *dev) > > > > pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, > > pci_grackle_config_write, s); > > - pci_mem_data = cpu_register_io_memory(pci_grackle_read, > > - pci_grackle_write, > > + pci_mem_data = cpu_register_io_memory(pci_host_data_read_mmio, > > + pci_host_data_write_mmio, > > &s->host_state); > > sysbus_init_mmio(dev, 0x1000, pci_mem_config); > > sysbus_init_mmio(dev, 0x1000, pci_mem_data); > > @@ -185,8 +171,8 @@ static int pci_dec_21154_init_device(SysBusDevice *dev) > > > > pci_mem_config = cpu_register_io_memory(pci_grackle_config_read, > > pci_grackle_config_write, s); > > - pci_mem_data = cpu_register_io_memory(pci_grackle_read, > > - pci_grackle_write, > > + pci_mem_data = cpu_register_io_memory(pci_host_data_read_mmio, > > + pci_host_data_write_mmio, > > &s->host_state); > > sysbus_init_mmio(dev, 0x1000, pci_mem_config); > > sysbus_init_mmio(dev, 0x1000, pci_mem_data); > > diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c > > index 8f9ae4a..fb7f5bd 100644 > > --- a/hw/gt64xxx.c > > +++ b/hw/gt64xxx.c > > @@ -25,10 +25,8 @@ > > #include "hw.h" > > #include "mips.h" > > #include "pci.h" > > -#include "pc.h" > > - > > -typedef target_phys_addr_t pci_addr_t; > > #include "pci_host.h" > > +#include "pc.h" > > > > //#define DEBUG > > > > @@ -1119,13 +1117,6 @@ PCIBus *pci_gt64120_init(qemu_irq *pic) > > GT64120State *s; > > PCIDevice *d; > > > > - (void)&pci_host_data_writeb; /* avoid warning */ > > - (void)&pci_host_data_writew; /* avoid warning */ > > - (void)&pci_host_data_writel; /* avoid warning */ > > - (void)&pci_host_data_readb; /* avoid warning */ > > - (void)&pci_host_data_readw; /* avoid warning */ > > - (void)&pci_host_data_readl; /* avoid warning */ > > - > > s = qemu_mallocz(sizeof(GT64120State)); > > s->pci = qemu_mallocz(sizeof(GT64120PCIState)); > > > > diff --git a/hw/pci_host.h b/hw/pci_host.c > > similarity index 69% > > copy from hw/pci_host.h > > copy to hw/pci_host.c > > index 48862b5..5c06f03 100644 > > --- a/hw/pci_host.h > > +++ b/hw/pci_host.c > > @@ -25,10 +25,13 @@ > > /* Worker routines for a PCI host controller that uses an {address,data} > > register pair to access PCI configuration space. */ > > > > +#ifndef PCI_HOST_C > > + > > /* debug PCI */ > > //#define DEBUG_PCI > > > > -#include "sysbus.h" > > +#include "pci.h" > > +#include "pci_host.h" > > > > #ifdef DEBUG_PCI > > #define PCI_DPRINTF(fmt, ...) \ > > @@ -37,13 +40,40 @@ do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0) > > #define PCI_DPRINTF(fmt, ...) > > #endif > > > > -typedef struct { > > - SysBusDevice busdev; > > - uint32_t config_reg; > > - PCIBus *bus; > > -} PCIHostState; > > +#define PCI_HOST_C > > + > > +#define PCI_ADDR_T target_phys_addr_t > > +#define PCI_HOST_SUFFIX _mmio > > +#define PCI_HOST_STATIC static > > + > > +#include "pci_host.c" > > + > > +CPUWriteMemoryFunc * const pci_host_data_write_mmio[] = { > > + &glue(pci_host_data_writeb, PCI_HOST_SUFFIX), > > + &glue(pci_host_data_writew, PCI_HOST_SUFFIX), > > + &glue(pci_host_data_writel, PCI_HOST_SUFFIX), > > +}; > > + > > +CPUReadMemoryFunc * const pci_host_data_read_mmio[] = { > > + &glue(pci_host_data_readb, PCI_HOST_SUFFIX), > > + &glue(pci_host_data_readw, PCI_HOST_SUFFIX), > > + &glue(pci_host_data_readl, PCI_HOST_SUFFIX), > > +}; > > + > > +#undef PCI_ADDR_T > > +#undef PCI_HOST_SUFFIX > > +#undef PCI_HOST_STATIC > > > > -static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val) > > +#define PCI_ADDR_T uint32_t > > +#define PCI_HOST_SUFFIX _ioport > > +#define PCI_HOST_STATIC /* nothing. export this function */ > > + > > +#include "pci_host.c" > > + > > +#else > > + > > +PCI_HOST_STATIC void glue(pci_host_data_writeb, PCI_HOST_SUFFIX)( > > + void* opaque, PCI_ADDR_T addr, uint32_t val) > > { > > PCIHostState *s = opaque; > > > > @@ -53,7 +83,8 @@ static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val) > > pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1); > > } > > > > -static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val) > > +PCI_HOST_STATIC void glue(pci_host_data_writew, PCI_HOST_SUFFIX)( > > + void* opaque, PCI_ADDR_T addr, uint32_t val) > > { > > PCIHostState *s = opaque; > > #ifdef TARGET_WORDS_BIGENDIAN > > @@ -65,7 +96,8 @@ static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val) > > pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2); > > } > > > > -static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val) > > +PCI_HOST_STATIC void glue(pci_host_data_writel, PCI_HOST_SUFFIX)( > > + void* opaque, PCI_ADDR_T addr, uint32_t val) > > { > > PCIHostState *s = opaque; > > #ifdef TARGET_WORDS_BIGENDIAN > > @@ -77,7 +109,8 @@ static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val) > > pci_data_write(s->bus, s->config_reg, val, 4); > > } > > > > -static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr) > > +PCI_HOST_STATIC uint32_t glue(pci_host_data_readb, PCI_HOST_SUFFIX)( > > + void* opaque, PCI_ADDR_T addr) > > { > > PCIHostState *s = opaque; > > uint32_t val; > > @@ -90,7 +123,8 @@ static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr) > > return val; > > } > > > > -static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr) > > +PCI_HOST_STATIC uint32_t glue(pci_host_data_readw, PCI_HOST_SUFFIX)( > > + void* opaque, PCI_ADDR_T addr) > > { > > PCIHostState *s = opaque; > > uint32_t val; > > @@ -105,7 +139,8 @@ static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr) > > return val; > > } > > > > -static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr) > > +PCI_HOST_STATIC uint32_t glue(pci_host_data_readl, PCI_HOST_SUFFIX)( > > + void* opaque, PCI_ADDR_T addr) > > { > > PCIHostState *s = opaque; > > uint32_t val; > > @@ -119,3 +154,5 @@ static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr) > > #endif > > return val; > > } > > + > > +#endif > > diff --git a/hw/pci_host.h b/hw/pci_host.h > > index 48862b5..ea98ed2 100644 > > --- a/hw/pci_host.h > > +++ b/hw/pci_host.h > > @@ -25,97 +25,27 @@ > > /* Worker routines for a PCI host controller that uses an {address,data} > > register pair to access PCI configuration space. */ > > > > -/* debug PCI */ > > -//#define DEBUG_PCI > > +#ifndef PCI_HOST_H > > +#define PCI_HOST_H > > > > #include "sysbus.h" > > > > -#ifdef DEBUG_PCI > > -#define PCI_DPRINTF(fmt, ...) \ > > -do { printf("pci_host_data: " fmt , ## __VA_ARGS__); } while (0) > > -#else > > -#define PCI_DPRINTF(fmt, ...) > > -#endif > > - > > typedef struct { > > SysBusDevice busdev; > > uint32_t config_reg; > > PCIBus *bus; > > } PCIHostState; > > > > -static void pci_host_data_writeb(void* opaque, pci_addr_t addr, uint32_t val) > > -{ > > - PCIHostState *s = opaque; > > - > > - PCI_DPRINTF("writeb addr " TARGET_FMT_plx " val %x\n", > > - (target_phys_addr_t)addr, val); > > - if (s->config_reg & (1u << 31)) > > - pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1); > > -} > > - > > -static void pci_host_data_writew(void* opaque, pci_addr_t addr, uint32_t val) > > -{ > > - PCIHostState *s = opaque; > > -#ifdef TARGET_WORDS_BIGENDIAN > > - val = bswap16(val); > > -#endif > > - PCI_DPRINTF("writew addr " TARGET_FMT_plx " val %x\n", > > - (target_phys_addr_t)addr, val); > > - if (s->config_reg & (1u << 31)) > > - pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2); > > -} > > - > > -static void pci_host_data_writel(void* opaque, pci_addr_t addr, uint32_t val) > > -{ > > - PCIHostState *s = opaque; > > -#ifdef TARGET_WORDS_BIGENDIAN > > - val = bswap32(val); > > -#endif > > - PCI_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n", > > - (target_phys_addr_t)addr, val); > > - if (s->config_reg & (1u << 31)) > > - pci_data_write(s->bus, s->config_reg, val, 4); > > -} > > - > > -static uint32_t pci_host_data_readb(void* opaque, pci_addr_t addr) > > -{ > > - PCIHostState *s = opaque; > > - uint32_t val; > > - > > - if (!(s->config_reg & (1 << 31))) > > - return 0xff; > > - val = pci_data_read(s->bus, s->config_reg | (addr & 3), 1); > > - PCI_DPRINTF("readb addr " TARGET_FMT_plx " val %x\n", > > - (target_phys_addr_t)addr, val); > > - return val; > > -} > > +/* for mmio */ > > +extern CPUWriteMemoryFunc * const pci_host_data_write_mmio[]; > > +extern CPUReadMemoryFunc * const pci_host_data_read_mmio[]; > > > > -static uint32_t pci_host_data_readw(void* opaque, pci_addr_t addr) > > -{ > > - PCIHostState *s = opaque; > > - uint32_t val; > > - if (!(s->config_reg & (1 << 31))) > > - return 0xffff; > > - val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2); > > - PCI_DPRINTF("readw addr " TARGET_FMT_plx " val %x\n", > > - (target_phys_addr_t)addr, val); > > -#ifdef TARGET_WORDS_BIGENDIAN > > - val = bswap16(val); > > -#endif > > - return val; > > -} > > +/* for ioio */ > > +void pci_host_data_writeb_ioport(void* opaque, uint32_t addr, uint32_t val); > > +void pci_host_data_writew_ioport(void* opaque, uint32_t addr, uint32_t val); > > +void pci_host_data_writel_ioport(void* opaque, uint32_t addr, uint32_t val); > > +uint32_t pci_host_data_readb_ioport(void* opaque, uint32_t addr); > > +uint32_t pci_host_data_readw_ioport(void* opaque, uint32_t addr); > > +uint32_t pci_host_data_readl_ioport(void* opaque, uint32_t addr); > > > > -static uint32_t pci_host_data_readl(void* opaque, pci_addr_t addr) > > -{ > > - PCIHostState *s = opaque; > > - uint32_t val; > > - if (!(s->config_reg & (1 << 31))) > > - return 0xffffffff; > > - val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4); > > - PCI_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", > > - (target_phys_addr_t)addr, val); > > -#ifdef TARGET_WORDS_BIGENDIAN > > - val = bswap32(val); > > -#endif > > - return val; > > -} > > +#endif /* PCI_HOST_H */ > > diff --git a/hw/piix_pci.c b/hw/piix_pci.c > > index edd6df0..c8db791 100644 > > --- a/hw/piix_pci.c > > +++ b/hw/piix_pci.c > > @@ -25,12 +25,10 @@ > > #include "hw.h" > > #include "pc.h" > > #include "pci.h" > > +#include "pci_host.h" > > #include "isa.h" > > #include "sysbus.h" > > > > -typedef uint32_t pci_addr_t; > > -#include "pci_host.h" > > - > > typedef PCIHostState I440FXState; > > > > typedef struct PIIX3State { > > @@ -201,12 +199,12 @@ static int i440fx_pcihost_initfn(SysBusDevice *dev) > > register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s); > > register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s); > > > > - register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s); > > - register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s); > > - register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s); > > - register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s); > > - register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s); > > - register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); > > + register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb_ioport, s); > > + register_ioport_write(0xcfc, 4, 2, pci_host_data_writew_ioport, s); > > + register_ioport_write(0xcfc, 4, 4, pci_host_data_writel_ioport, s); > > + register_ioport_read(0xcfc, 4, 1, pci_host_data_readb_ioport, s); > > + register_ioport_read(0xcfc, 4, 2, pci_host_data_readw_ioport, s); > > + register_ioport_read(0xcfc, 4, 4, pci_host_data_readl_ioport, s); > > return 0; > > } > > > > diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c > > index 655fe86..953e6b6 100644 > > --- a/hw/ppc4xx_pci.c > > +++ b/hw/ppc4xx_pci.c > > @@ -22,8 +22,6 @@ > > #include "hw.h" > > #include "ppc.h" > > #include "ppc4xx.h" > > - > > -typedef target_phys_addr_t pci_addr_t; > > #include "pci.h" > > #include "pci_host.h" > > #include "bswap.h" > > @@ -117,18 +115,6 @@ static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = { > > &pci4xx_cfgaddr_writel, > > }; > > > > -static CPUReadMemoryFunc * const pci4xx_cfgdata_read[] = { > > - &pci_host_data_readb, > > - &pci_host_data_readw, > > - &pci_host_data_readl, > > -}; > > - > > -static CPUWriteMemoryFunc * const pci4xx_cfgdata_write[] = { > > - &pci_host_data_writeb, > > - &pci_host_data_writew, > > - &pci_host_data_writel, > > -}; > > - > > static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, > > uint32_t value) > > { > > @@ -392,8 +378,8 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], > > cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); > > > > /* CFGDATA */ > > - index = cpu_register_io_memory(pci4xx_cfgdata_read, > > - pci4xx_cfgdata_write, > > + index = cpu_register_io_memory(pci_host_data_read_mmio, > > + pci_host_data_write_mmio, > > &controller->pci_state); > > if (index < 0) > > goto free; > > diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c > > index 64fccfd..4920837 100644 > > --- a/hw/ppce500_pci.c > > +++ b/hw/ppce500_pci.c > > @@ -17,7 +17,6 @@ > > #include "hw.h" > > #include "ppc.h" > > #include "ppce500.h" > > -typedef target_phys_addr_t pci_addr_t; > > #include "pci.h" > > #include "pci_host.h" > > #include "bswap.h" > > @@ -116,18 +115,6 @@ static CPUWriteMemoryFunc * const pcie500_cfgaddr_write[] = { > > &pcie500_cfgaddr_writel, > > }; > > > > -static CPUReadMemoryFunc * const pcie500_cfgdata_read[] = { > > - &pci_host_data_readb, > > - &pci_host_data_readw, > > - &pci_host_data_readl, > > -}; > > - > > -static CPUWriteMemoryFunc * const pcie500_cfgdata_write[] = { > > - &pci_host_data_writeb, > > - &pci_host_data_writew, > > - &pci_host_data_writel, > > -}; > > - > > static uint32_t pci_reg_read4(void *opaque, target_phys_addr_t addr) > > { > > PPCE500PCIState *pci = opaque; > > @@ -344,8 +331,8 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers) > > cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index); > > > > /* CFGDATA */ > > - index = cpu_register_io_memory(pcie500_cfgdata_read, > > - pcie500_cfgdata_write, > > + index = cpu_register_io_memory(pci_host_data_read_mmio, > > + pci_host_data_write_mmio, > > &controller->pci_state); > > if (index < 0) > > goto free; > > diff --git a/hw/prep_pci.c b/hw/prep_pci.c > > index 2d8a0fa..943de90 100644 > > --- a/hw/prep_pci.c > > +++ b/hw/prep_pci.c > > @@ -24,8 +24,6 @@ > > > > #include "hw.h" > > #include "pci.h" > > - > > -typedef uint32_t pci_addr_t; > > #include "pci_host.h" > > > > typedef PCIHostState PREPPCIState; > > @@ -144,12 +142,12 @@ PCIBus *pci_prep_init(qemu_irq *pic) > > register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s); > > register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s); > > > > - register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s); > > - register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s); > > - register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s); > > - register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s); > > - register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s); > > - register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); > > + register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb_ioport, s); > > + register_ioport_write(0xcfc, 4, 2, pci_host_data_writew_ioport, s); > > + register_ioport_write(0xcfc, 4, 4, pci_host_data_writel_ioport, s); > > + register_ioport_read(0xcfc, 4, 1, pci_host_data_readb_ioport, s); > > + register_ioport_read(0xcfc, 4, 2, pci_host_data_readw_ioport, s); > > + register_ioport_read(0xcfc, 4, 4, pci_host_data_readl_ioport, s); > > > > PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read, > > PPC_PCIIO_write, s); > > diff --git a/hw/unin_pci.c b/hw/unin_pci.c > > index a202153..1d11816 100644 > > --- a/hw/unin_pci.c > > +++ b/hw/unin_pci.c > > @@ -24,6 +24,7 @@ > > #include "hw.h" > > #include "ppc_mac.h" > > #include "pci.h" > > +#include "pci_host.h" > > > > /* debug UniNorth */ > > //#define DEBUG_UNIN > > @@ -35,9 +36,6 @@ > > #define UNIN_DPRINTF(fmt, ...) > > #endif > > > > -typedef target_phys_addr_t pci_addr_t; > > -#include "pci_host.h" > > - > > typedef struct UNINState { > > SysBusDevice busdev; > > PCIHostState host_state; > > @@ -83,18 +81,6 @@ static CPUReadMemoryFunc * const pci_unin_main_config_read[] = { > > &pci_unin_main_config_readl, > > }; > > > > -static CPUWriteMemoryFunc * const pci_unin_main_write[] = { > > - &pci_host_data_writeb, > > - &pci_host_data_writew, > > - &pci_host_data_writel, > > -}; > > - > > -static CPUReadMemoryFunc * const pci_unin_main_read[] = { > > - &pci_host_data_readb, > > - &pci_host_data_readw, > > - &pci_host_data_readl, > > -}; > > - > > static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr, > > uint32_t val) > > { > > @@ -123,18 +109,6 @@ static CPUReadMemoryFunc * const pci_unin_config_read[] = { > > &pci_unin_config_readl, > > }; > > > > -static CPUWriteMemoryFunc * const pci_unin_write[] = { > > - &pci_host_data_writeb, > > - &pci_host_data_writew, > > - &pci_host_data_writel, > > -}; > > - > > -static CPUReadMemoryFunc * const pci_unin_read[] = { > > - &pci_host_data_readb, > > - &pci_host_data_readw, > > - &pci_host_data_readl, > > -}; > > - > > /* Don't know if this matches real hardware, but it agrees with OHW. */ > > static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num) > > { > > @@ -180,8 +154,9 @@ static int pci_unin_main_init_device(SysBusDevice *dev) > > > > pci_mem_config = cpu_register_io_memory(pci_unin_main_config_read, > > pci_unin_main_config_write, s); > > - pci_mem_data = cpu_register_io_memory(pci_unin_main_read, > > - pci_unin_main_write, &s->host_state); > > + pci_mem_data = cpu_register_io_memory(pci_host_data_read_mmio, > > + pci_host_data_write_mmio, > > + &s->host_state); > > > > sysbus_init_mmio(dev, 0x1000, pci_mem_config); > > sysbus_init_mmio(dev, 0x1000, pci_mem_data); > > @@ -203,8 +178,9 @@ static int pci_dec_21154_init_device(SysBusDevice *dev) > > // XXX: s = &pci_bridge[2]; > > pci_mem_config = cpu_register_io_memory(pci_unin_config_read, > > pci_unin_config_write, s); > > - pci_mem_data = cpu_register_io_memory(pci_unin_main_read, > > - pci_unin_main_write, &s->host_state); > > + pci_mem_data = cpu_register_io_memory(pci_host_data_read_mmio, > > + pci_host_data_write_mmio, > > + &s->host_state); > > sysbus_init_mmio(dev, 0x1000, pci_mem_config); > > sysbus_init_mmio(dev, 0x1000, pci_mem_data); > > return 0; > > @@ -220,8 +196,9 @@ static int pci_unin_agp_init_device(SysBusDevice *dev) > > > > pci_mem_config = cpu_register_io_memory(pci_unin_config_read, > > pci_unin_config_write, s); > > - pci_mem_data = cpu_register_io_memory(pci_unin_main_read, > > - pci_unin_main_write, &s->host_state); > > + pci_mem_data = cpu_register_io_memory(pci_host_data_read_mmio, > > + pci_host_data_write_mmio, > > + &s->host_state); > > sysbus_init_mmio(dev, 0x1000, pci_mem_config); > > sysbus_init_mmio(dev, 0x1000, pci_mem_data); > > return 0; > > @@ -237,8 +214,8 @@ static int pci_unin_internal_init_device(SysBusDevice *dev) > > > > pci_mem_config = cpu_register_io_memory(pci_unin_config_read, > > pci_unin_config_write, s); > > - pci_mem_data = cpu_register_io_memory(pci_unin_read, > > - pci_unin_write, s); > > + pci_mem_data = cpu_register_io_memory(pci_host_data_read_mmio, > > + pci_host_data_write_mmio, s); > > sysbus_init_mmio(dev, 0x1000, pci_mem_config); > > sysbus_init_mmio(dev, 0x1000, pci_mem_data); > > return 0; > > -- > > 1.6.0.2