[Qemu-devel] Re: [Qemu-commits] [COMMIT c0b1905] qemu/pci: reset device registers on bus reset

["Michael S. Tsirkin" <mst@redhat.com>]

On Wed, Oct 07, 2009 at 10:20:19AM +0200, Avi Kivity wrote:
> On 10/05/2009 04:53 PM, Anthony Liguori wrote:
>> From: Michael S. Tsirkin<mst@redhat.com>
>>
>> Reset BARs and a couple of other registers on bus reset, as per PCI
>> spec.
>>    
>
> This commit breaks Windows XP restart.  After a restart Windows switches  
> from 800x600 cirrus logic vga to 640x480 standard vga.  My guess is that  
> this is due to two mutually-cancelling bugs:
>
> - the bios fails to initialize one of the registers touched below
> - qemu sets up that register in the state the Windows expects the bios  
> to leave it in instead of the on-reset state

Yes, cirrus does this on init:
     pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
Trying to understand what's the right thing to do is.

> Once we perform the reset the register reverts to its correct reset  
> state, the bios fails to initialize it, and Windows ignores the device.
>
> I reverted this commit from qemu-kvm.git.
>
>> diff --git a/hw/pci.c b/hw/pci.c
>> index 2dd7213..e2f88ff 100644
>> --- a/hw/pci.c
>> +++ b/hw/pci.c
>> @@ -92,7 +92,20 @@ static inline int pci_bar(int reg)
>>
>>   static void pci_device_reset(PCIDevice *dev)
>>   {
>> +    int r;
>> +
>>       memset(dev->irq_state, 0, sizeof dev->irq_state);
>> +    dev->config[PCI_COMMAND]&= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
>> +                                  PCI_COMMAND_MASTER);
>> +    dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
>> +    dev->config[PCI_INTERRUPT_LINE] = 0x0;
>> +    for (r = 0; r<  PCI_NUM_REGIONS; ++r) {
>> +        if (!dev->io_regions[r].size) {
>> +            continue;
>> +        }
>> +        pci_set_long(dev->config + pci_bar(r), dev->io_regions[r].type);
>> +    }
>> +    pci_update_mappings(dev);
>>   }
>>
>>   static void pci_bus_reset(void *opaque)
>>
>>
>>    
>
>
> -- 
> Do not meddle in the internals of kernels, for they are subtle and quick to panic.