From: "Michael S. Tsirkin" <mst@redhat.com>
To: Isaku Yamahata <yamahata@valinux.co.jp>
Cc: qemu-devel@nongnu.org
Subject: [Qemu-devel] Re: [PATCH V5 14/29] pci: introduce FMT_PCIBUS for printf format for pcibus_t.
Date: Sat, 10 Oct 2009 21:32:44 +0200 [thread overview]
Message-ID: <20091010193244.GC14275@redhat.com> (raw)
In-Reply-To: <1255069742-15724-15-git-send-email-yamahata@valinux.co.jp>
On Fri, Oct 09, 2009 at 03:28:47PM +0900, Isaku Yamahata wrote:
> This patch is preliminary for 64bit BAR.
> Later pcibus_t will be changed from uint32_t to uint64_t.
> Introduce FMT_PCIBUS for printf format for pcibus_t.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/e1000.c | 6 ++++--
> hw/eepro100.c | 6 ++++--
> hw/pci.c | 14 +++++++++-----
> hw/pci.h | 1 +
> hw/pcnet.c | 6 ++++--
> hw/wdt_i6300esb.c | 3 ++-
> 6 files changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/hw/e1000.c b/hw/e1000.c
> index aa84f31..9056e2f 100644
> --- a/hw/e1000.c
> +++ b/hw/e1000.c
> @@ -145,7 +145,8 @@ static void
> ioport_map(PCIDevice *pci_dev, int region_num, pcibus_t addr,
> pcibus_t size, int type)
> {
> - DBGOUT(IO, "e1000_ioport_map addr=0x%04x size=0x%08x\n", addr, size);
> + DBGOUT(IO, "e1000_ioport_map addr=0x%04"FMT_PCIBUS
> + " size=0x%08"FMT_PCIBUS"\n", addr, size);
> }
>
> static void
> @@ -1040,7 +1041,8 @@ e1000_mmio_map(PCIDevice *pci_dev, int region_num,
> };
>
>
> - DBGOUT(MMIO, "e1000_mmio_map addr=0x%08x 0x%08x\n", addr, size);
> + DBGOUT(MMIO, "e1000_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
> + addr, size);
>
> cpu_register_physical_memory(addr, PNPMMIO_SIZE, d->mmio_index);
> qemu_register_coalesced_mmio(addr, excluded_regs[0]);
> diff --git a/hw/eepro100.c b/hw/eepro100.c
> index 1a9e96e..da41b73 100644
> --- a/hw/eepro100.c
> +++ b/hw/eepro100.c
> @@ -1398,7 +1398,8 @@ static void pci_map(PCIDevice * pci_dev, int region_num,
> {
> EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
>
> - TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
> + TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
> + "size=0x%08"FMT_PCIBUS", type=%d\n",
> region_num, addr, size, type));
>
> assert(region_num == 1);
> @@ -1477,7 +1478,8 @@ static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
> {
> EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
>
> - TRACE(OTHER, logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
> + TRACE(OTHER, logout("region %d, addr=0x%08"FMT_PCIBUS", "
> + "size=0x%08"FMT_PCIBUS", type=%d\n",
> region_num, addr, size, type));
>
> if (region_num == 0) {
> diff --git a/hw/pci.c b/hw/pci.c
> index 6d46e5b..c0ae66a 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -467,7 +467,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
>
> if (size & (size-1)) {
> fprintf(stderr, "ERROR: PCI region size must be pow2 "
> - "type=0x%x, size=0x%x\n", type, size);
> + "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
> exit(1);
> }
>
> @@ -484,7 +484,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
> wmask |= PCI_ROM_ADDRESS_ENABLE;
> }
> pci_set_long(pci_dev->config + addr, type);
> - pci_set_long(pci_dev->wmask + addr, wmask);
> + pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
> pci_set_long(pci_dev->cmask + addr, 0xffffffff);
> }
>
> @@ -762,10 +762,12 @@ static void pci_info_device(PCIDevice *d)
> if (r->size != 0) {
> monitor_printf(mon, " BAR%d: ", i);
> if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
> - monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
> + monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
> + " [0x%04"FMT_PCIBUS"].\n",
> r->addr, r->addr + r->size - 1);
> } else {
> - monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
> + monitor_printf(mon, "32 bit memory at 0x%08"FMT_PCIBUS
> + " [0x%08"FMT_PCIBUS"].\n",
> r->addr, r->addr + r->size - 1);
> }
> }
> @@ -1112,7 +1114,9 @@ static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
> r = &d->io_regions[i];
> if (!r->size)
> continue;
> - monitor_printf(mon, "%*sbar %d: %s at 0x%x [0x%x]\n", indent, "",
> + monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
> + " [0x%"FMT_PCIBUS"]\n",
> + indent, "",
> i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
> r->addr, r->addr + r->size - 1);
> }
> diff --git a/hw/pci.h b/hw/pci.h
> index 7d3911d..8a187c2 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -72,6 +72,7 @@ extern target_phys_addr_t pci_mem_base;
> #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
>
> typedef uint32_t pcibus_t;
> +#define FMT_PCIBUS PRIx32
>
> typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
> uint32_t address, uint32_t data, int len);
> diff --git a/hw/pcnet.c b/hw/pcnet.c
> index e9d2d73..6102e1a 100644
> --- a/hw/pcnet.c
> +++ b/hw/pcnet.c
> @@ -1764,7 +1764,8 @@ static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
> PCNetState *d = &DO_UPCAST(PCIPCNetState, pci_dev, pci_dev)->state;
>
> #ifdef PCNET_DEBUG_IO
> - printf("pcnet_ioport_map addr=0x%04x size=0x%04x\n", addr, size);
> + printf("pcnet_ioport_map addr=0x%04"FMT_PCIBUS" size=0x%04"FMT_PCIBUS"\n",
> + addr, size);
> #endif
>
> register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
> @@ -1990,7 +1991,8 @@ static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num,
> PCIPCNetState *d = DO_UPCAST(PCIPCNetState, pci_dev, pci_dev);
>
> #ifdef PCNET_DEBUG_IO
> - printf("pcnet_mmio_map addr=0x%08x 0x%08x\n", addr, size);
> + printf("pcnet_mmio_map addr=0x%08"FMT_PCIBUS" 0x%08"FMT_PCIBUS"\n",
> + addr, size);
> #endif
>
> cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->state.mmio_index);
> diff --git a/hw/wdt_i6300esb.c b/hw/wdt_i6300esb.c
> index 76f5dd9..9621035 100644
> --- a/hw/wdt_i6300esb.c
> +++ b/hw/wdt_i6300esb.c
> @@ -362,7 +362,8 @@ static void i6300esb_map(PCIDevice *dev, int region_num,
> I6300State *d = DO_UPCAST(I6300State, dev, dev);
> int io_mem;
>
> - i6300esb_debug("addr = %x, size = %x, type = %d\n", addr, size, type);
> + i6300esb_debug("addr = %"FMT_PCIBUS", size = %"FMT_PCIBUS", type = %d\n",
> + addr, size, type);
>
> io_mem = cpu_register_io_memory(mem_read, mem_write, d);
> cpu_register_physical_memory (addr, 0x10, io_mem);
> --
> 1.6.0.2
next prev parent reply other threads:[~2009-10-10 19:34 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-09 6:28 [Qemu-devel] [PATCH V5 00/29] pci: various pci clean up and pci express support Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 01/29] pci: fix PCI_DPRINTF() wrt variadic macro Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 02/29] pci: introduce constant PCI_NUM_PINS for the number of interrupt pins, 4 Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 03/29] pci: use PCI_SLOT() and PCI_FUNC() Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 04/29] pci: define a constant to represent a unmapped bar and use it Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 05/29] pci: helper functions to access PCIDevice::config Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 06/29] pci: use helper functions to access pci config space Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 07/29] pci/bridge: clean up of pci_bridge_initfn() Isaku Yamahata
2009-10-09 6:53 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-13 13:20 ` Isaku Yamahata
2009-10-13 14:17 ` Michael S. Tsirkin
2009-10-13 15:12 ` Blue Swirl
2009-10-13 15:26 ` Michael S. Tsirkin
2009-10-13 16:32 ` Blue Swirl
2009-10-09 6:54 ` Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 08/29] pci: s/PCI_ADDRESS_SPACE_/PCI_BASE_ADDRESS_SPACE_/ to match pci_regs.h Isaku Yamahata
2009-10-09 6:57 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-13 13:21 ` Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 09/29] pci: clean up of pci_default_read_config Isaku Yamahata
2009-10-09 6:50 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-09 6:58 ` Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 10/29] pci: make pci_bar() aware of header type 1 Isaku Yamahata
2009-10-09 7:06 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-10 19:29 ` Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 11/29] pci_host.h: move functions in pci_host.h into .c file Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 12/29] pci_host: consolidate pci config address access Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 13/29] pci: introduce pcibus_t to represent pci bus address/size instead of uint32_t Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 14/29] pci: introduce FMT_PCIBUS for printf format for pcibus_t Isaku Yamahata
2009-10-10 19:32 ` Michael S. Tsirkin [this message]
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 15/29] pci: typedef pcibus_t as uint64_t instead of uint32_t Isaku Yamahata
2009-10-11 10:43 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-13 13:31 ` Isaku Yamahata
2009-10-13 14:39 ` Michael S. Tsirkin
2009-10-14 4:35 ` Isaku Yamahata
2009-10-14 8:55 ` Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 16/29] pci: 64bit bar support Isaku Yamahata
2009-10-10 19:39 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-13 13:52 ` Isaku Yamahata
2009-10-13 15:00 ` Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 17/29] pci: make pci configuration transaction more accurate Isaku Yamahata
2009-10-09 12:52 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 18/29] pci: factor out the conversion logic from io port address into pci device Isaku Yamahata
2009-10-10 19:41 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 19/29] pci: split out ioport address parsing from pci configuration access logic Isaku Yamahata
2009-10-10 19:45 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-13 14:14 ` Isaku Yamahata
2009-10-13 14:49 ` Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 20/29] pci: move pci host stuff from pci.c to pci_host.c Isaku Yamahata
2009-10-10 19:46 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 21/29] pci_host: change the signature of pci_data_{read, write} Isaku Yamahata
2009-10-09 12:02 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 22/29] vmstate: add VMSTATE_ARRAY_POINTER for pointer to array Isaku Yamahata
2009-10-11 10:37 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 23/29] pci: pcie host and mmcfg support Isaku Yamahata
2009-10-11 10:26 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 24/29] pci: fix pci_default_write_config() Isaku Yamahata
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 25/29] pci: add helper functions for pci config write function Isaku Yamahata
2009-10-10 19:58 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-09 6:28 ` [Qemu-devel] [PATCH V5 26/29] pci: use helper function in pci_default_write_config() Isaku Yamahata
2009-10-09 6:29 ` [Qemu-devel] [PATCH V5 27/29] pci/bridge: don't update bar mapping when bar2-5 is changed Isaku Yamahata
2009-10-09 10:35 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-09 6:29 ` [Qemu-devel] [PATCH V5 28/29] pci: initialize pci config headers depending it pci header type Isaku Yamahata
2009-10-09 10:42 ` [Qemu-devel] " Michael S. Tsirkin
2009-10-13 14:31 ` Isaku Yamahata
2009-10-13 14:52 ` Michael S. Tsirkin
2009-10-13 15:06 ` Michael S. Tsirkin
2009-10-09 6:29 ` [Qemu-devel] [PATCH V5 29/29] pci/monitor: print out bridge's filtering values and so on Isaku Yamahata
2009-10-10 20:05 ` [Qemu-devel] " Michael S. Tsirkin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20091010193244.GC14275@redhat.com \
--to=mst@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=yamahata@valinux.co.jp \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).