From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Mx6Of-0006cT-LG for qemu-devel@nongnu.org; Sun, 11 Oct 2009 17:56:09 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1Mx6Oa-0006VN-OA for qemu-devel@nongnu.org; Sun, 11 Oct 2009 17:56:09 -0400 Received: from [199.232.76.173] (port=50886 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Mx6Oa-0006V0-IC for qemu-devel@nongnu.org; Sun, 11 Oct 2009 17:56:04 -0400 Received: from mx1.redhat.com ([209.132.183.28]:20303) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Mx6Oa-0002kM-1b for qemu-devel@nongnu.org; Sun, 11 Oct 2009 17:56:04 -0400 Date: Sun, 11 Oct 2009 23:53:56 +0200 From: "Michael S. Tsirkin" Message-ID: <20091011215356.GC6411@redhat.com> References: <1255287547-28329-1-git-send-email-gleb@redhat.com> <1255287547-28329-3-git-send-email-gleb@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1255287547-28329-3-git-send-email-gleb@redhat.com> Subject: [Qemu-devel] Re: [PATCH 3/5] Use the correct mask to size the PCI option ROM BAR. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gleb Natapov Cc: kevin@koconnor.net, qemu-devel@nongnu.org On Sun, Oct 11, 2009 at 08:59:05PM +0200, Gleb Natapov wrote: > Bit 0 is the enable bit, which we not only don't want to set, but > it will stick and make us think it's an I/O port resource. > > Qemu pcbios commit 6ddb9f5c742b2b82b1755d7ec2a127f6e20e3806 > > Signed-off-by: Gleb Natapov > --- > src/pciinit.c | 8 +++++--- > 1 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/src/pciinit.c b/src/pciinit.c > index 1d0f784..29b3901 100644 > --- a/src/pciinit.c > +++ b/src/pciinit.c > @@ -139,11 +139,13 @@ static void pci_bios_init_device(u16 bdf) > int ofs; > u32 val, size; > > - if (i == PCI_ROM_SLOT) > + if (i == PCI_ROM_SLOT) { > ofs = PCI_ROM_ADDRESS; > - else > + pci_config_writel(bdf, ofs, 0xfffffffe); > + } else { > ofs = PCI_BASE_ADDRESS_0 + i * 4; > - pci_config_writel(bdf, ofs, 0xffffffff); > + pci_config_writel(bdf, ofs, 0xffffffff); > + } > val = pci_config_readl(bdf, ofs); > if (val != 0) { > size = (~(val & ~0xf)) + 1; Hmm, eithe rinterpreet the spec strictly or loosely. If you implement the spec loosely, you can just write 0xfffffffe unconditionally: low bit is readonly for i/o and memory. Strict interpretation of spec requires that you write 0 into reserved bits. These are bits 1 to 10 for ROM, and bit 1 for I/O. > -- > 1.6.3.3 > >