From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MxKxz-0003uX-Ow for qemu-devel@nongnu.org; Mon, 12 Oct 2009 09:29:35 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MxKxu-0003qb-EC for qemu-devel@nongnu.org; Mon, 12 Oct 2009 09:29:34 -0400 Received: from [199.232.76.173] (port=35428 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MxKxu-0003qV-96 for qemu-devel@nongnu.org; Mon, 12 Oct 2009 09:29:30 -0400 Received: from mx1.redhat.com ([209.132.183.28]:3591) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MxKxt-0005TR-6K for qemu-devel@nongnu.org; Mon, 12 Oct 2009 09:29:29 -0400 Date: Mon, 12 Oct 2009 15:29:25 +0200 From: Gleb Natapov Message-ID: <20091012132925.GA3026@redhat.com> References: <1255287547-28329-3-git-send-email-gleb@redhat.com> <20091011215356.GC6411@redhat.com> <20091012065024.GS16702@redhat.com> <20091012095225.GA11741@redhat.com> <20091012100821.GE16702@redhat.com> <20091012110335.GA12546@redhat.com> <20091012114841.GF16702@redhat.com> <20091012115916.GA12834@redhat.com> <20091012120857.GI16702@redhat.com> <20091012132025.GA13022@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20091012132025.GA13022@redhat.com> Subject: [Qemu-devel] Re: [PATCH 3/5] Use the correct mask to size the PCI option ROM BAR. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: kevin@koconnor.net, qemu-devel@nongnu.org On Mon, Oct 12, 2009 at 03:20:27PM +0200, Michael S. Tsirkin wrote: > Right. And there's another bug that I see and that is that size for I/O > BAR was calculated incorrectly: val & ~0xf is wrong for I/O as the size > could be 4 bytes. So here's a patch that addresses all 3 issues: > Ack? > Pleas do whatever spec recommends and use 0xffffffff to size the BAR. Specs says this, linux does this, lets not be different. > > ----> > > Subject: [PATCH] seabios: fix low bits in ROM and I/O sizing > > This cleans up handling of low bits during BAR sizing, > to match PCI spec requirements, and to use symbolic > constants from pci_regs.h > > Issues fixed: > For ROM BARs, bit 0 is writeable (enable bit), which we not > only don't want to set, but it will stick and make us think > it's an I/O port resource. > Further, PCI spec defines the following bits as reserved: > - bit 1 in I/O BAR > - bits 10:1 in ROM BAR > and we should be careful and preserve any values there. > Bits 3:2 in I/O BAR might be writeable, so it > is wrong to mask them when calculating BAR size. > > Spec references: > See 6.2.5.1 for I/O and memory, and 6.2.5.2 for ROM, > 6.1 for reserved bit handling; > pages 225, 228 and 214 in PCI spec revision 3.0. > > See also Qemu pcbios commit 6ddb9f5c742b2b82b1755d7ec2a127f6e20e3806 > > Original-by: Gleb Natapov > Signed-off-by: Michael S. Tsirkin > > diff --git a/src/pciinit.c b/src/pciinit.c > index 7d2ea00..f9ebd61 100644 > --- a/src/pciinit.c > +++ b/src/pciinit.c > @@ -136,16 +136,23 @@ static void pci_bios_init_device(u16 bdf) > /* default memory mappings */ > for (i = 0; i < PCI_NUM_REGIONS; i++) { > int ofs; > - u32 val, size; > - > + u32 val, mask, size; > if (i == PCI_ROM_SLOT) > ofs = PCI_ROM_ADDRESS; > else > ofs = PCI_BASE_ADDRESS_0 + i * 4; > - pci_config_writel(bdf, ofs, 0xffffffff); > + > + val = pci_config_readl(bdf, ofs); > + if (i == PCI_ROM_SLOT) > + mask = PCI_ROM_ADDRESS_MASK; > + else if (val & PCI_BASE_ADDRESS_SPACE_IO) > + mask = PCI_BASE_ADDRESS_IO_MASK; > + else > + mask = PCI_BASE_ADDRESS_MEM_MASK; > + pci_config_writel(bdf, ofs, val | mask); > val = pci_config_readl(bdf, ofs); > if (val != 0) { > - size = (~(val & ~0xf)) + 1; > + size = (~(val & mask)) + 1; > if (val & PCI_BASE_ADDRESS_SPACE_IO) > paddr = &pci_bios_io_addr; > else if (size >= 0x04000000) > -- > 1.6.5.rc2 > -- Gleb.