From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1MxzgJ-0006Si-LU for qemu-devel@nongnu.org; Wed, 14 Oct 2009 04:58:03 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1MxzgE-0006KG-EC for qemu-devel@nongnu.org; Wed, 14 Oct 2009 04:58:02 -0400 Received: from [199.232.76.173] (port=35719 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1MxzgE-0006K0-2R for qemu-devel@nongnu.org; Wed, 14 Oct 2009 04:57:58 -0400 Received: from mx1.redhat.com ([209.132.183.28]:19568) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1MxzgD-0006iR-Fo for qemu-devel@nongnu.org; Wed, 14 Oct 2009 04:57:57 -0400 Date: Wed, 14 Oct 2009 10:55:46 +0200 From: "Michael S. Tsirkin" Message-ID: <20091014085546.GA23038@redhat.com> References: <1255069742-15724-1-git-send-email-yamahata@valinux.co.jp> <1255069742-15724-16-git-send-email-yamahata@valinux.co.jp> <20091011104312.GA15590@redhat.com> <20091013133133.GE2306%yamahata@valinux.co.jp> <20091013143914.GB17895@redhat.com> <20091014043549.GL2306%yamahata@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20091014043549.GL2306%yamahata@valinux.co.jp> Subject: [Qemu-devel] Re: [PATCH V5 15/29] pci: typedef pcibus_t as uint64_t instead of uint32_t. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: qemu-devel@nongnu.org On Wed, Oct 14, 2009 at 01:35:49PM +0900, Isaku Yamahata wrote: > On Tue, Oct 13, 2009 at 04:39:15PM +0200, Michael S. Tsirkin wrote: > > On Tue, Oct 13, 2009 at 10:31:33PM +0900, Isaku Yamahata wrote: > > > On Sun, Oct 11, 2009 at 12:43:12PM +0200, Michael S. Tsirkin wrote: > > > > On Fri, Oct 09, 2009 at 03:28:48PM +0900, Isaku Yamahata wrote: > > > > > This patch is preliminary for 64bit bar. > > > > > For 64bit bar support, change pcibus_t which represents > > > > > pci bus addr/size from uint32_t to uint64_t. > > > > > And also change FMT_pcibus for printf. > > > > > > > > > > In pci_update_mapping() checks 32bit overflow. > > > > > So the check must be updated too. > > > > > > > > > > Signed-off-by: Isaku Yamahata > > > > > > > > That's all fine, but if you look at users implementing > > > > map io, they do: cpu_register_physical_memory() > > > > on the address they are given. And if target_phys_addr_t is 32 bit, > > > > this will silently truncate the address. > > > > > > > > So I would like to understand how this will all > > > > work on 32 bit systems. > > > > > > The case is > > > . BAR is memory 64bit and > > > . target_phys_addr_t is 32bit and > > > . bar is set to >4G. > > > Hmm, the case isn't checked. > > > > > > It would be checked by > > > - last_addr <= new_addr > > > + (target_phys_addr_t)last_addr <= new_addr > > > > That's pretty tricky. Can we just convert everything into > > 64 bit unconditionally and just do simple range checks? > > > > > > > > I'll fix it with comments added. Nice catch. > > > > Is this the right thing to do though? > > I think 32 bit CPU might address something like 64G > > memory of highmem support, so a 64 bit value might > > actually be valid. > > > > Let's step back and understand what the motivation is? > > Maybe declaring all bars as 32 bit for 32 bit targets is enough? > > It is independent of guest OS for PCI device to have 64 bit BAR. > It is valid to use PCI card with 64bit bar on 32 bit OS. Yes, but qemu does not support this yet. > In that case > the OS will set the 64 bit bar within addressable region. > And it is allowed for 32 bit OS to set 64bit BAR to >4GB. > (which doesn't make sense, though.) Yes, it does. E.g. with high memory, a 32 bit OS can address more than 4G RAM. > > How about adding the following check? > last_addr >= TARGET_PHYS_ADDR_MAX And then what? > -- > yamahata