From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N2QVV-0000ip-Km for qemu-devel@nongnu.org; Mon, 26 Oct 2009 10:25:13 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N2QVQ-0000fr-Ev for qemu-devel@nongnu.org; Mon, 26 Oct 2009 10:25:12 -0400 Received: from [199.232.76.173] (port=52892 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N2QVQ-0000fl-9X for qemu-devel@nongnu.org; Mon, 26 Oct 2009 10:25:08 -0400 Received: from mx1.redhat.com ([209.132.183.28]:1047) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N2QVP-0003QD-Tr for qemu-devel@nongnu.org; Mon, 26 Oct 2009 10:25:08 -0400 Date: Mon, 26 Oct 2009 16:22:44 +0200 From: "Michael S. Tsirkin" Message-ID: <20091026142244.GA25423@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH] qemu/msix: fix table access issues List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Juan Quintela Cc: qemu-devel@nongnu.org Fixes a couple of issues with msix table access: - With misbehaving guests, misaligned 4 byte access could overflow msix table and cause qemu to segfault. Since PCI spec requires host to only issue dword-aligned accesses, as a fix, it's enough to mask the address low bits. - Tables use pci format, not native format, and so we must use pci_[sg]et_long on read/write. Reported-by: Juan Quintela Signed-off-by: Michael S. Tsirkin --- Tested with x86 guest. hw/msix.c | 11 ++++------- 1 files changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/msix.c b/hw/msix.c index b0dea91..3d67c4e 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -128,13 +128,10 @@ void msix_write_config(PCIDevice *dev, uint32_t addr, static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr) { PCIDevice *dev = opaque; - unsigned int offset = addr & (MSIX_PAGE_SIZE - 1); + unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3; void *page = dev->msix_table_page; - uint32_t val = 0; - memcpy(&val, (void *)((char *)page + offset), 4); - - return val; + return pci_get_long(page + offset); } static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr) @@ -178,9 +175,9 @@ static void msix_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { PCIDevice *dev = opaque; - unsigned int offset = addr & (MSIX_PAGE_SIZE - 1); + unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3; int vector = offset / MSIX_ENTRY_SIZE; - memcpy(dev->msix_table_page + offset, &val, 4); + pci_set_long(dev->msix_table_page + offset, val); if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) { msix_clr_pending(dev, vector); msix_notify(dev, vector); -- 1.6.5.rc2