From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N2han-0000KJ-As for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:39:49 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N2ham-0000Ig-5E for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:39:48 -0400 Received: from [199.232.76.173] (port=38770 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N2ham-0000IS-11 for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:39:48 -0400 Received: from hall.aurel32.net ([88.191.82.174]:43631) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1N2hal-00008E-Ka for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:39:47 -0400 Date: Tue, 27 Oct 2009 09:39:42 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH v2 05/10] target-arm: optimize arm load/store multiple ops Message-ID: <20091027083942.GA4399@hall.aurel32.net> References: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> <1256386749-85299-6-git-send-email-juha.riihimaki@nokia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1256386749-85299-6-git-send-email-juha.riihimaki@nokia.com> Sender: Aurelien Jarno List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: juha.riihimaki@nokia.com Cc: qemu-devel@nongnu.org On Sat, Oct 24, 2009 at 03:19:04PM +0300, juha.riihimaki@nokia.com wrote: > From: Juha Riihimäki > > RM load/store multiple instructions can be slightly optimized by > loading the register offset constant into a variable outside the > register loop and using the preloaded variable inside the loop instead > of reloading the offset value to a temporary variable on each loop > iteration. This causes less TCG ops to be generated for a ARM load/ > store multiple instruction if there are more than one register > accessed, otherwise the number of generated TCG ops is the same. > > Signed-off-by: Juha Riihimäki > Acked-by: Laurent Desnogues This patch breaks, the boot of an arm kernel, as tmp2 is used elsewhere within this code path. OTOH, while it reduce the number of TCG ops, that should not impact the generated host asm code, as most (all ?) targets are able to add a small constant value to a register in one instruction. > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 38fb833..d1e2ed2 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -6852,6 +6852,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) > } > rn = (insn >> 16) & 0xf; > addr = load_reg(s, rn); > + tmp2 = tcg_const_i32(4); > > /* compute total size */ > loaded_base = 0; > @@ -6865,7 +6866,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) > if (insn & (1 << 23)) { > if (insn & (1 << 24)) { > /* pre increment */ > - tcg_gen_addi_i32(addr, addr, 4); > + tcg_gen_add_i32(addr, addr, tmp2); > } else { > /* post increment */ > } > @@ -6918,7 +6919,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) > j++; > /* no need to add after the last transfer */ > if (j != n) > - tcg_gen_addi_i32(addr, addr, 4); > + tcg_gen_add_i32(addr, addr, tmp2); > } > } > if (insn & (1 << 21)) { > @@ -6928,7 +6929,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) > /* pre increment */ > } else { > /* post increment */ > - tcg_gen_addi_i32(addr, addr, 4); > + tcg_gen_add_i32(addr, addr, tmp2); > } > } else { > if (insn & (1 << 24)) { > @@ -6944,6 +6945,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) > } else { > dead_tmp(addr); > } > + tcg_temp_free_i32(tmp2); > if (loaded_base) { > store_reg(s, rn, loaded_var); > } > -- > 1.6.5 > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net