From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N2hd9-0001W0-KA for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:42:15 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N2hd8-0001Vi-UW for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:42:15 -0400 Received: from [199.232.76.173] (port=38839 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N2hd8-0001VW-Ov for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:42:14 -0400 Received: from hall.aurel32.net ([88.191.82.174]:51992) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1N2hd8-0000We-5n for qemu-devel@nongnu.org; Tue, 27 Oct 2009 04:42:14 -0400 Date: Tue, 27 Oct 2009 09:42:12 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH v2 04/10] target-arm: optimize vfp load/store multiple ops Message-ID: <20091027084212.GB4399@hall.aurel32.net> References: <1256386749-85299-1-git-send-email-juha.riihimaki@nokia.com> <1256386749-85299-5-git-send-email-juha.riihimaki@nokia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1256386749-85299-5-git-send-email-juha.riihimaki@nokia.com> Sender: Aurelien Jarno List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: juha.riihimaki@nokia.com Cc: qemu-devel@nongnu.org On Sat, Oct 24, 2009 at 03:19:03PM +0300, juha.riihimaki@nokia.com wrote: > From: Juha Riihimäki > > VFP load/store multiple instructions can be slightly optimized by > loading the register offset constant into a variable outside the > register loop and using the preloaded variable inside the loop instead > of reloading the offset value to a temporary variable on each loop > iteration. This causes less TCG ops to be generated for a VFP load/ > store multiple instruction if there are more than one register > accessed, otherwise the amount of generated TCG ops is the same. Same for this patch, it should not change the generated host code, so I am not sure it really worth it. > Signed-off-by: Juha Riihimäki > --- > target-arm/translate.c | 4 +++- > 1 files changed, 3 insertions(+), 1 deletions(-) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 8cb1c0f..38fb833 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -3222,6 +3222,7 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) > offset = 8; > else > offset = 4; > + tmp = tcg_const_i32(offset); > for (i = 0; i < n; i++) { > if (insn & ARM_CP_RW_BIT) { > /* load */ > @@ -3232,8 +3233,9 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) > gen_mov_F0_vreg(dp, rd + i); > gen_vfp_st(s, dp, addr); > } > - tcg_gen_addi_i32(addr, addr, offset); > + tcg_gen_add_i32(addr, addr, tmp); > } > + tcg_temp_free_i32(tmp); > if (insn & (1 << 21)) { > /* writeback */ > if (insn & (1 << 24)) > -- > 1.6.5 > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net