From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N5K73-0005Bn-0S for qemu-devel@nongnu.org; Tue, 03 Nov 2009 09:11:58 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N5K6w-00059r-JQ for qemu-devel@nongnu.org; Tue, 03 Nov 2009 09:11:55 -0500 Received: from [199.232.76.173] (port=32947 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N5K6u-00059I-6h for qemu-devel@nongnu.org; Tue, 03 Nov 2009 09:11:49 -0500 Received: from mx1.redhat.com ([209.132.183.28]:65287) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N5K6t-0005wZ-Qh for qemu-devel@nongnu.org; Tue, 03 Nov 2009 09:11:48 -0500 Date: Tue, 3 Nov 2009 16:09:16 +0200 From: "Michael S. Tsirkin" Subject: Re: [Qemu-devel] Re: [PATCH V6 17/32] pci: 64bit bar support. Message-ID: <20091103140916.GB5605@redhat.com> References: <1256905286-25435-1-git-send-email-yamahata@valinux.co.jp> <1256905286-25435-18-git-send-email-yamahata@valinux.co.jp> <20091101160730.GA21894@redhat.com> <20091103035210.GA28390%yamahata@valinux.co.jp> <20091103114756.GC3375@redhat.com> <4AF0206F.7080004@redhat.com> <20091103123906.GB4961@redhat.com> <20091103140100.GB28390%yamahata@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20091103140100.GB28390%yamahata@valinux.co.jp> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: Avi Kivity , qemu-devel@nongnu.org On Tue, Nov 03, 2009 at 11:01:00PM +0900, Isaku Yamahata wrote: > On Tue, Nov 03, 2009 at 02:39:06PM +0200, Michael S. Tsirkin wrote: > > On Tue, Nov 03, 2009 at 02:22:07PM +0200, Avi Kivity wrote: > > > On 11/03/2009 01:47 PM, Michael S. Tsirkin wrote: > > >> > > >> If qemu is compiled with target phys address size 32 bit, emulated > > >> devices can not support a 64 bit BAR. Therefore, according to PCI spec, > > >> such devices should declare all BARs as 32 bit. > > Here is the point. > > "emulated devices can not support a 64 bit BAR" > If target_phy_addr_t = uint32_t, the emulation of 64 bit BAR which > is set to >4GB is cpu can't access it. So just not-mapping it > is correct behavior. > > > > > What happens if you take a PCI card that supports 64-bit BARs and stick > > > it into a machine that has a 32-bit physical address space? > > > The firmware/OS will configure the BARs to below 4G. > > > > > >> I think you are right that guests on such systems really do not have a > > >> way to address PCI devices if BAR is set beyond 4G. But pci emulation is > > >> better off not relying on this, IMO. Makes sense? > > >> > > > > > > No. Device emulation shouldn't change with the machine type. > > > > I agree. Issue is, we recompile the *devices* as well. > > It's the device emulation that is broken when compiled > > with target phys addr set to 32 bit, because all devices > > take pcibus_t and cast it to target_phys_addr_t > > and then do stuff with it. > > So such emulation should not claim to support 64 bit. > > Such case is checked by "last_addr >= TARGET_PHYS_ADDR_MAX", > so the device emulation works well. > > Generally device drivers know their devices. For example they know > that BAR0 is 64bit memory and so on. So if BAR type were changed > by forcing 64 bit BAR into 32 bit BAR, the device driver wouldn't be > confused. > > > Long term, we should fix all devices and *then* they can claim 64 bit > > support always. As a nice side effect, we'll be able to avoid > > rebuilding devices. > > Are you claiming that (PCI) devices emulation shouldn't depend on > target_phys_addr_t? That sounds a good idea. Yes. Maybe we can stop devices from mapping memory, have pci core do it for them. > However I don't agree on "*then*". > The conversions would take place step by step as it's long term object. > I don't see any reason to penalize correct device emulations just > because there are incomplete device emulations left. Hmm. Okay ... but which device emulations are correct? It seems that none of them are. I don't see the rush . > thanks, > -- > yamahata