From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1N8XFU-0002on-8w for qemu-devel@nongnu.org; Thu, 12 Nov 2009 05:49:56 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1N8XFP-0002hx-FL for qemu-devel@nongnu.org; Thu, 12 Nov 2009 05:49:55 -0500 Received: from [199.232.76.173] (port=52517 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1N8XFO-0002hZ-Ff for qemu-devel@nongnu.org; Thu, 12 Nov 2009 05:49:50 -0500 Received: from mx1.redhat.com ([209.132.183.28]:41374) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1N8XFN-00057h-Vg for qemu-devel@nongnu.org; Thu, 12 Nov 2009 05:49:50 -0500 Date: Thu, 12 Nov 2009 12:47:17 +0200 From: "Michael S. Tsirkin" Message-ID: <20091112104717.GO3785@redhat.com> References: <1258005528-25383-1-git-send-email-yamahata@valinux.co.jp> <1258005528-25383-20-git-send-email-yamahata@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1258005528-25383-20-git-send-email-yamahata@valinux.co.jp> Subject: [Qemu-devel] Re: [PATCH 19/20] pci: pci bridge related clean up. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: qemu-devel@nongnu.org On Thu, Nov 12, 2009 at 02:58:47PM +0900, Isaku Yamahata wrote: > - fix bridge prefetchable memory accesser to check 64bit or not. > - use pcibus_t consistently instead mixing pcibus_t and uint64_t. > > Signed-off-by: Isaku Yamahata Acked-by: Michael S. Tsirkin > --- > hw/pci.c | 18 +++++++++++------- > hw/pci.h | 1 + > 2 files changed, 12 insertions(+), 7 deletions(-) > > diff --git a/hw/pci.c b/hw/pci.c > index d1b884a..add919b 100644 > --- a/hw/pci.c > +++ b/hw/pci.c > @@ -634,19 +634,23 @@ static uint32_t pci_config_get_io_base(PCIDevice *d, > return val; > } > > -static uint64_t pci_config_get_memory_base(PCIDevice *d, uint32_t base) > +static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base) > { > - return ((uint64_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) > + return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK) > << 16; > } > > -static uint64_t pci_config_get_pref_base(PCIDevice *d, > +static pcibus_t pci_config_get_pref_base(PCIDevice *d, > uint32_t base, uint32_t upper) > { > - uint64_t val; > - val = ((uint64_t)pci_get_word(d->config + base) & > - PCI_PREF_RANGE_MASK) << 16; > - val |= (uint64_t)pci_get_long(d->config + upper) << 32; > + pcibus_t tmp; > + pcibus_t val; > + > + tmp = (pcibus_t)pci_get_word(d->config + base); > + val = (tmp & PCI_PREF_RANGE_MASK) << 16; > + if (tmp & PCI_PREF_RANGE_TYPE_64) { > + val |= (pcibus_t)pci_get_long(d->config + upper) << 32; > + } > return val; > } > > diff --git a/hw/pci.h b/hw/pci.h > index 72a476e..03639b7 100644 > --- a/hw/pci.h > +++ b/hw/pci.h > @@ -131,6 +131,7 @@ typedef struct PCIIORegion { > #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */ > #define PCI_PREF_MEMORY_LIMIT 0x26 > #define PCI_PREF_RANGE_MASK (~0x0fUL) > +#define PCI_PREF_RANGE_TYPE_64 0x01 > #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */ > #define PCI_PREF_LIMIT_UPPER32 0x2c > #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ > -- > 1.6.0.2