From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NCWtw-000672-O4 for qemu-devel@nongnu.org; Mon, 23 Nov 2009 06:16:12 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NCWtr-00064o-KL for qemu-devel@nongnu.org; Mon, 23 Nov 2009 06:16:12 -0500 Received: from [199.232.76.173] (port=41005 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NCWtq-00064Z-Vj for qemu-devel@nongnu.org; Mon, 23 Nov 2009 06:16:07 -0500 Received: from mx1.redhat.com ([209.132.183.28]:7081) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NCWtq-0002G9-Du for qemu-devel@nongnu.org; Mon, 23 Nov 2009 06:16:06 -0500 Date: Mon, 23 Nov 2009 13:16:01 +0200 From: Gleb Natapov Subject: Re: [Qemu-devel] Re: POST failure (loop) with isapc and seabios Message-ID: <20091123111601.GH2999@redhat.com> References: <20091120225113.GD24539@morn.localdomain> <20091122123503.GH3193@redhat.com> <20091122151052.GK3193@redhat.com> <20091122153842.GA13491@morn.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20091122153842.GA13491@morn.localdomain> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Kevin O'Connor Cc: qemu-devel@nongnu.org, Sebastian Herbszt On Sun, Nov 22, 2009 at 10:38:42AM -0500, Kevin O'Connor wrote: > On Sun, Nov 22, 2009 at 05:10:53PM +0200, Gleb Natapov wrote: > > On Sun, Nov 22, 2009 at 04:07:56PM +0100, Sebastian Herbszt wrote: > > > Gleb Natapov wrote: > > > >May be make qemu to map it writable if isapc is specified. > > > > > > I don't think keeping the segment writable after POST is a good idea. > > > > > Isn't it writable now after POST with pcipc? Why this is not a good > > idea? > > SeaBIOS and bochs bios will make the f-segment readonly at the end of > post. See make_bios_readonly() in src/shadow.c. > I see SeaBIOS does this, but I don't see where bochs bios does this. > SeaBIOS' ram locking requires the same pci access that the unlocking > needs, so if qemu made the f-segment writable on isa then it would > remain writable past POST. > > -Kevin -- Gleb.