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Date: Mon, 23 Nov 2009 21:18:00 +0200
From: Gleb Natapov <gleb@redhat.com>
Subject: Re: [Qemu-devel] Re: POST failure (loop) with isapc and seabios
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To: Sebastian Herbszt <herbszt@gmx.de>
Cc: Kevin O'Connor <kevin@koconnor.net>, qemu-devel@nongnu.org

On Mon, Nov 23, 2009 at 08:12:32PM +0100, Sebastian Herbszt wrote:
> Gleb Natapov wrote:
> >On Mon, Nov 23, 2009 at 06:57:47PM +0100, Sebastian Herbszt wrote:
> >>Gleb Natapov wrote:
> >>>On Sun, Nov 22, 2009 at 10:38:42AM -0500, Kevin O'Connor wrote:
> >>>>On Sun, Nov 22, 2009 at 05:10:53PM +0200, Gleb Natapov wrote:
> >>>>> On Sun, Nov 22, 2009 at 04:07:56PM +0100, Sebastian Herbszt wrote:
> >>>>> > Gleb Natapov wrote:
> >>>>> > >May be make qemu to map it writable if isapc is specified.
> >>>>> > > > I don't think keeping the segment writable after POST is
> >>>>a good idea.
> >>>>> > > Isn't it writable now after POST with pcipc? Why this is
> >>>>not a good
> >>>>> idea?
> >>>>
> >>>>SeaBIOS and bochs bios will make the f-segment readonly at the end of
> >>>>post.  See make_bios_readonly() in src/shadow.c.
> >>>>
> >>>I see SeaBIOS does this, but I don't see where bochs bios does this.
> >>
> >>bios_lock_shadow_ram() in rombio32.c.
> >>
> >This functions is called far from end of the post and it doesn't change
> >mapping to be read only as far as I can see.
> 
> Bochs bios only keeps the memory writable inside rombios32. bios_lock_shadow_ram()
> clears the upper 4 bits (7:4) and then sets bit 4 to 1 making the value of the bit pair 5:4
> (pci register 0x59) 01 being read only.
> 
Ah correct. I missed that read/write status is in bits 7:4 not 0:3.

--
			Gleb.