From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NDGFg-0006OH-Aq for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:40 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NDGFa-0006Lo-Ug for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:39 -0500 Received: from [199.232.76.173] (port=54734 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NDGFa-0006Lf-Kd for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:34 -0500 Received: from mx1.redhat.com ([209.132.183.28]:4574) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NDGFZ-00012z-W8 for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:34 -0500 Date: Wed, 25 Nov 2009 13:38:55 +0200 From: "Michael S. Tsirkin" Message-ID: <20091125113855.GB9322@redhat.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: [Qemu-devel] [PATCH 1/5] msix: fix mask bit state after reset List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, anthony@codemonkey.ws PCI spec states that mask bit must be 1 after reset. Make it so. Signed-off-by: Michael S. Tsirkin --- hw/msix.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/hw/msix.c b/hw/msix.c index d499441..45f83dd 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -217,6 +217,15 @@ void msix_mmio_map(PCIDevice *d, int region_num, d->msix_mmio_index); } +static void msix_mask_all(struct PCIDevice *dev, unsigned nentries) +{ + int vector; + for (vector = 0; vector < nentries; ++vector) { + unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL; + dev->msix_table_page[offset] |= MSIX_VECTOR_MASK; + } +} + /* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is * modified, it should be retrieved with msix_bar_size. */ int msix_init(struct PCIDevice *dev, unsigned short nentries, @@ -234,6 +243,7 @@ int msix_init(struct PCIDevice *dev, unsigned short nentries, sizeof *dev->msix_entry_used); dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE); + msix_mask_all(dev, nentries); dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read, msix_mmio_write, dev); @@ -353,6 +363,7 @@ void msix_reset(PCIDevice *dev) msix_free_irq_entries(dev); dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK; memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE); + msix_mask_all(dev, dev->msix_entries_nr); } /* PCI spec suggests that devices make it possible for software to configure -- 1.6.5.2.143.g8cc62