From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NDGFo-0006Sv-Fr for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:48 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NDGFj-0006Q4-Nj for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:47 -0500 Received: from [199.232.76.173] (port=54742 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NDGFj-0006Pv-CQ for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:43 -0500 Received: from mx1.redhat.com ([209.132.183.28]:11006) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NDGFi-00014K-Qd for qemu-devel@nongnu.org; Wed, 25 Nov 2009 06:41:43 -0500 Date: Wed, 25 Nov 2009 13:39:03 +0200 From: "Michael S. Tsirkin" Message-ID: <20091125113903.GC9322@redhat.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: [Qemu-devel] [PATCH 2/5] msix: fix reset value for enable bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, anthony@codemonkey.ws On reset, we currently clear all bits in msix control register *except* enable bit. This is wrong: the spec says we should clear writeable bits: function mask and enable bit. Correct this. Signed-off-by: Michael S. Tsirkin --- hw/msix.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/hw/msix.c b/hw/msix.c index 45f83dd..785e097 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -361,7 +361,8 @@ void msix_reset(PCIDevice *dev) if (!(dev->cap_present & QEMU_PCI_CAP_MSIX)) return; msix_free_irq_entries(dev); - dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK; + dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= + ~dev->wmask[dev->msix_cap + MSIX_ENABLE_OFFSET]; memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE); msix_mask_all(dev, dev->msix_entries_nr); } -- 1.6.5.2.143.g8cc62