From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NDLFU-0004EZ-QQ for qemu-devel@nongnu.org; Wed, 25 Nov 2009 12:01:49 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NDLFO-0004Bq-Rr for qemu-devel@nongnu.org; Wed, 25 Nov 2009 12:01:47 -0500 Received: from [199.232.76.173] (port=42653 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NDLFN-0004BZ-0r for qemu-devel@nongnu.org; Wed, 25 Nov 2009 12:01:42 -0500 Received: from mx1.redhat.com ([209.132.183.28]:30971) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NDLFM-0003uq-DB for qemu-devel@nongnu.org; Wed, 25 Nov 2009 12:01:40 -0500 Date: Wed, 25 Nov 2009 18:58:59 +0200 From: "Michael S. Tsirkin" Message-ID: <20091125165859.GD24783@redhat.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: [Qemu-devel] [PATCH 3/4] pci: interrupt status bit implementation List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, anthony@codemonkey.ws, yamahata@valinux.co.jp interrupt status is a mandatory feature in PCI spec, so devices must implement it to be spec compliant. Signed-off-by: Michael S. Tsirkin --- hw/pci.c | 22 ++++++++++++++++++++++ hw/pci.h | 1 + 2 files changed, 23 insertions(+), 0 deletions(-) diff --git a/hw/pci.c b/hw/pci.c index 7717461..844664b 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -103,12 +103,24 @@ static int pci_bar(PCIDevice *d, int reg) return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; } +/* Update interrupt status bit in config space on interrupt + * state change. */ +static void pci_update_irq_status(PCIDevice *dev) +{ + if (dev->irq_status) { + dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; + } else { + dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; + } +} + static void pci_device_reset(PCIDevice *dev) { int r; memset(dev->irq_state, 0, sizeof dev->irq_state); dev->irq_status = 0; + pci_update_irq_status(dev); dev->config[PCI_COMMAND] &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); dev->config[PCI_CACHE_LINE_SIZE] = 0x0; @@ -314,7 +326,14 @@ static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s) void pci_device_save(PCIDevice *s, QEMUFile *f) { + /* Clear interrupt status bit: it is implicit + * in irq_state which we are saving. + * This makes us compatible with old devices + * which never set or clear this bit. */ + s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; vmstate_save_state(f, pci_get_vmstate(s), s); + /* Restore the interrupt status bit. */ + pci_update_irq_status(s); } int pci_device_load(PCIDevice *s, QEMUFile *f) @@ -324,6 +343,8 @@ int pci_device_load(PCIDevice *s, QEMUFile *f) for (i = 0; i < ARRAY_SIZE(s->irq_state); ++i) { s->irq_status += s->irq_state[i]; } + /* Restore the interrupt status bit. */ + pci_update_irq_status(s); return ret; } @@ -914,6 +935,7 @@ static void pci_set_irq(void *opaque, int irq_num, int level) pci_dev->irq_state[irq_num] = level; pci_dev->irq_status += change; + pci_update_irq_status(s); pci_change_irq_level(pci_dev, irq_num, change); } diff --git a/hw/pci.h b/hw/pci.h index 2e172f6..c3f2c3f 100644 --- a/hw/pci.h +++ b/hw/pci.h @@ -102,6 +102,7 @@ typedef struct PCIIORegion { #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ #define PCI_COMMAND_MASTER 0x4 /* Enable bus master */ #define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_INTERRUPT 0x08 #define PCI_REVISION_ID 0x08 /* 8 bits */ #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */ #define PCI_CLASS_DEVICE 0x0a /* Device class */ -- 1.6.5.2.143.g8cc62