From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NDgcn-0007og-Ts for qemu-devel@nongnu.org; Thu, 26 Nov 2009 10:51:17 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NDgci-0007i2-J1 for qemu-devel@nongnu.org; Thu, 26 Nov 2009 10:51:16 -0500 Received: from [199.232.76.173] (port=55576 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NDgci-0007hn-C8 for qemu-devel@nongnu.org; Thu, 26 Nov 2009 10:51:12 -0500 Received: from mx1.redhat.com ([209.132.183.28]:57990) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NDgci-0001Pu-2G for qemu-devel@nongnu.org; Thu, 26 Nov 2009 10:51:12 -0500 Date: Thu, 26 Nov 2009 17:48:23 +0200 From: "Michael S. Tsirkin" Message-ID: <20091126154823.GA2694@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCHv2 0/3] pci: interrupt status/interrupt disable support List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, anthony@codemonkey.ws, yamahata@valinux.co.jp, paul@codesourcery.com, quintela@redhat.com This patchset adds support for mandatory interupt status and interrupt disable bits to all PCI devices. This is required for PCI compliancy. These patches are on top of my pci tree, including Isaku Yamahata's fixes. If this is a problem, let me know and I will rebase. This works fine for me, but since this touches all PCI devices, please review carefully. Changes from v1: - Addressed review comments: get rid of irq_state and irq_disabled fields in PCI device as suggested by Paul Brook and Isaku Yamahata. Michael S. Tsirkin (3): pci: prepare irq code for interrupt state pci: interrupt status bit implementation pci: interrupt disable bit support hw/pci.c | 144 +++++++++++++++++++++++++++++++++++++++++++++++++++++-------- hw/pci.h | 4 +- 2 files changed, 128 insertions(+), 20 deletions(-)