From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NFBug-00052c-W0 for qemu-devel@nongnu.org; Mon, 30 Nov 2009 14:27:59 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NFBug-00051y-7i for qemu-devel@nongnu.org; Mon, 30 Nov 2009 14:27:58 -0500 Received: from [199.232.76.173] (port=51154 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NFBug-00051t-3b for qemu-devel@nongnu.org; Mon, 30 Nov 2009 14:27:58 -0500 Received: from hall.aurel32.net ([88.191.82.174]:52856) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NFBuf-0001tA-9A for qemu-devel@nongnu.org; Mon, 30 Nov 2009 14:27:57 -0500 Date: Mon, 30 Nov 2009 18:45:23 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 01/11] target-mips: add ISAMode bits for mips16 execution Message-ID: <20091130174523.GA12314@volta.aurel32.net> References: <1259009409-2755-1-git-send-email-froydnj@codesourcery.com> <1259009409-2755-2-git-send-email-froydnj@codesourcery.com> <20091128101720.GA6391@volta.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <20091128101720.GA6391@volta.aurel32.net> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nathan Froyd Cc: qemu-devel@nongnu.org On Sat, Nov 28, 2009 at 11:17:20AM +0100, Aurelien Jarno wrote: > On Mon, Nov 23, 2009 at 12:49:59PM -0800, Nathan Froyd wrote: > > > > Signed-off-by: Nathan Froyd > > --- > > target-mips/cpu.h | 1 + > > target-mips/translate.c | 2 ++ > > 2 files changed, 3 insertions(+), 0 deletions(-) > > > > diff --git a/target-mips/cpu.h b/target-mips/cpu.h > > index 82f9a38..e8febe6 100644 > > --- a/target-mips/cpu.h > > +++ b/target-mips/cpu.h > > @@ -167,6 +167,7 @@ struct TCState { > > target_ulong CP0_TCContext; > > target_ulong CP0_TCSchedule; > > target_ulong CP0_TCScheFBack; > > + uint32_t ISAMode; /* MIPS32 or MIPS16 mode */ > > int32_t CP0_Debug_tcstatus; > > }; > > I am fine with this. > > > diff --git a/target-mips/translate.c b/target-mips/translate.c > > index e9d9224..b0a1b29 100644 > > --- a/target-mips/translate.c > > +++ b/target-mips/translate.c > > @@ -463,6 +463,7 @@ typedef struct DisasContext { > > struct TranslationBlock *tb; > > target_ulong pc, saved_pc; > > uint32_t opcode; > > + int isa_mode; > > int singlestep_enabled; > > /* Routine used to access memory */ > > int mem_idx; > > @@ -8306,6 +8307,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, > > ctx.pc = pc_start; > > ctx.saved_pc = -1; > > ctx.singlestep_enabled = env->singlestep_enabled; > > + ctx.isa_mode = env->active_tc.ISAMode; > > ctx.tb = tb; > > ctx.bstate = BS_NONE; > > /* Restore delay slot state from the tb context. */ > > Instead of a new ctx value, it's probably better to use a new bit in > hflags. It is also necessary to change MIPS_HFLAG_TMASK accordingly, to > ensure a MIPS16 translation block is not later executed while ISAMode is > 0 (while it should generate an exception) and vice-versa. > > This also mean that hflags should be recomputed each time ISAMode is > changed. > Actually just changing ctx.hflags is enough, as it is automatically saved to env->hflags at the end of the TB or if an exception can occur. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net