From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NK9iF-00027h-SX for qemu-devel@nongnu.org; Mon, 14 Dec 2009 07:07:40 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NK9iB-00026a-QE for qemu-devel@nongnu.org; Mon, 14 Dec 2009 07:07:39 -0500 Received: from [199.232.76.173] (port=50953 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NK9iB-00026T-H3 for qemu-devel@nongnu.org; Mon, 14 Dec 2009 07:07:35 -0500 Received: from mx20.gnu.org ([199.232.41.8]:61947) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NK9iA-0000Nq-Ta for qemu-devel@nongnu.org; Mon, 14 Dec 2009 07:07:35 -0500 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NK9iA-000648-6g for qemu-devel@nongnu.org; Mon, 14 Dec 2009 07:07:34 -0500 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] correcting ARM CPSR register bit position comment Date: Mon, 14 Dec 2009 12:07:22 +0000 References: <1260788953-30794-1-git-send-email-nemesisofstate@gmail.com> In-Reply-To: <1260788953-30794-1-git-send-email-nemesisofstate@gmail.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Message-Id: <200912141207.22651.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: nemesisofstate > - uint32_t VF; /* V is the bit 31. All other bits are undefined */ > + uint32_t VF; /* V is the bit 28. */ No. The original comment is correct. Paul