From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NMeVk-0007Lw-TR for qemu-devel@nongnu.org; Mon, 21 Dec 2009 04:25:04 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NMeVj-0007Ko-UA for qemu-devel@nongnu.org; Mon, 21 Dec 2009 04:25:04 -0500 Received: from [199.232.76.173] (port=54455 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NMeVj-0007Kf-Pc for qemu-devel@nongnu.org; Mon, 21 Dec 2009 04:25:03 -0500 Received: from hall.aurel32.net ([88.191.82.174]:40465) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NMeVj-0006kT-Cu for qemu-devel@nongnu.org; Mon, 21 Dec 2009 04:25:03 -0500 Date: Mon, 21 Dec 2009 10:24:55 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] PPC64: Fix timebase Message-ID: <20091221092455.GA4990@volta.aurel32.net> References: <1261354932-28003-1-git-send-email-agraf@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1261354932-28003-1-git-send-email-agraf@suse.de> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: qemu-devel@nongnu.org On Mon, Dec 21, 2009 at 01:22:12AM +0100, Alexander Graf wrote: > On PPC we have a 64-bit time base. Usually (PPC32) this is accessed using > two separate 32 bit SPR accesses to SPR_TBU and SPR_TBL. > > On PPC64 the SPR_TBL register acts as 64 bit though, so we get the full > 64 bits as return value. If we only take the lower ones, fine. But Linux > wants to see all 64 bits or it breaks. Good catch! However, I think this patch it's not fully complete and can be improved a bit - it's probably better to return a target_ulong value from cpu_ppc_load_tbl() with an explicit cast here, so that we don't have an implicit cast from 64-bit to 32-bit on qemu-system-powerpc (GCC may warn on that with some flags or in future versions). - the store function also has to be fixed. - the same changes should be done for the alternate timebase. > This patch makes PPC64 Linux work even after TB crossed the 32-bit boundary, > which usually happened a few seconds after bootup. > > Signed-off-by: Alexander Graf > > --- > > To verify my assumptions of the above I used this test program: > > int main() > { > unsigned int tbu=0, tbl=0; > unsigned long tb=0; > > asm("mftbu %0" : "=r" (tbu)); > asm("mftbl %0" : "=r" (tbl)); > asm("mftbl %0" : "=r" (tb)); > > printf("TB: %#x %#x\n", tbu, tbl); > printf("TB64: %#lx\n", tb); > } > > It produces the following output on a 970MP CPU: > > $ ./mftb > TB: 0x238 0xd676bd6 > TB64: 0x2380d676f75 > --- > hw/ppc.c | 4 ++-- > target-ppc/cpu.h | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/hw/ppc.c b/hw/ppc.c > index 5208039..b4bf2d3 100644 > --- a/hw/ppc.c > +++ b/hw/ppc.c > @@ -401,7 +401,7 @@ static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, > return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset; > } > > -uint32_t cpu_ppc_load_tbl (CPUState *env) > +uint64_t cpu_ppc_load_tbl (CPUState *env) > { > ppc_tb_t *tb_env = env->tb_env; > uint64_t tb; > @@ -409,7 +409,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env) > tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset); > LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); > > - return tb & 0xFFFFFFFF; > + return tb; > } > > static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 2535cbc..2dc301d 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -741,7 +741,7 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def); > > /* Time-base and decrementer management */ > #ifndef NO_CPU_IO_DEFS > -uint32_t cpu_ppc_load_tbl (CPUPPCState *env); > +uint64_t cpu_ppc_load_tbl (CPUPPCState *env); > uint32_t cpu_ppc_load_tbu (CPUPPCState *env); > void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value); > void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value); > -- > 1.6.0.2 > > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net