From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NSFVs-0003G9-Ip for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:56:20 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NSFVe-00034e-QB for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:56:13 -0500 Received: from [199.232.76.173] (port=43136 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NSFVb-00031A-Ei for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:56:03 -0500 Received: from mx20.gnu.org ([199.232.41.8]:36481) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NSFVX-0005JJ-HY for qemu-devel@nongnu.org; Tue, 05 Jan 2010 14:55:59 -0500 Received: from mx1.redhat.com ([209.132.183.28]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NRvQ6-0002Un-LF for qemu-devel@nongnu.org; Mon, 04 Jan 2010 17:29:03 -0500 Date: Tue, 5 Jan 2010 00:25:36 +0200 From: "Michael S. Tsirkin" Subject: Re: [Qemu-devel] Re: [PATCH 1/6] Make config space accessor host bus trapable Message-ID: <20100104222535.GA21659@redhat.com> References: <472F306A-0699-401C-8E6A-8E79B86E4C95@suse.de> <1262551822.2173.267.camel@pasglop> <19BFDDD5-85E0-42EC-9D71-391CECC023F5@suse.de> <20100104104516.GD4672@valinux.co.jp> <20100104110758.GE8522@redhat.com> <1262635858.2173.371.camel@pasglop> <20100104211208.GA21488@redhat.com> <1262640330.2173.386.camel@pasglop> <20100104213021.GC21488@redhat.com> <1262642032.2173.388.camel@pasglop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1262642032.2173.388.camel@pasglop> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: Blue Swirl , Isaku Yamahata , Alexander Graf , Aurelien Jarno , QEMU Developers On Tue, Jan 05, 2010 at 08:53:52AM +1100, Benjamin Herrenschmidt wrote: > > > Yes, but I think how you program your host to pci bridge is platform specific, > > the standard (mostly) applies to what happens below the bridge. There's > > no real standard for how PCI host bridge is connected to processor > > AFAIK, it's by luck we can share code there at all. > > Well, yes and no ... there's a standard on how a PCI host bridge is > connected in the sense that how normal MMIO accesses go through in term > of endianness is well defined. > Go through where? From processor to PCI? Which spec do you refer to? > How you actually issue config space cycles is a property of a given > bridge. How you issue IO cycles as well in fact. > > Cheers, > Ben.