[Qemu-devel] [PATCH 0/9] sparc64: interrupts and tick timers v1

["Igor V. Kovalenko" <igor.v.kovalenko@gmail.com>]

The following series is a cleanup over previous one.

v0 -> v1: post-review changes
- dropped patch "clear exception_index with -1 val" (applied)
- new patch "change_pstate should have 32bit argument"
- cleanups for coding style and hexadecimal output convention
- wrpil is no-op for CONFIG_USER_ONLY
- restored PIL 15 as non-maskable interrupt level on sparcv8
- check for PSTATE.IE is replaced with call to cpu_interrupts_enabled()
- in patch "sparc64: interrupt trap handling"
  cleaned up change in cpu_exec; since sparc64 does not use
  CPU_INTERRUPT_TIMER now, corresponding code branch is unchanged

---

Igor V. Kovalenko (9):
      sparc64: change_pstate should have 32bit argument
      sparc64: trace pstate and global register set changes
      sparc64: add PIL to cpu state dump
      sparc64: use helper_wrpil to check pending irq on write
      sparc64: check for pending irq when pil, pstate or softint is changed
      sparc64: add macros to deal with softint and timer interrupt
      sparc64: move cpu_interrupts_enabled to cpu.h
      sparc64: interrupt trap handling
      sparc64: reimplement tick timers


 cpu-exec.c               |   28 +++---
 hw/sun4u.c               |  225 +++++++++++++++++++++++++++++++++++++---------
 target-sparc/cpu.h       |   27 ++++++
 target-sparc/exec.h      |   13 ---
 target-sparc/helper.c    |    1 
 target-sparc/helper.h    |    1 
 target-sparc/op_helper.c |   81 +++++++++++++++--
 target-sparc/translate.c |    5 -
 8 files changed, 300 insertions(+), 81 deletions(-)

-- 
Kind regards,
Igor V. Kovalenko