From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NSyxZ-0004Ej-Qj for qemu-devel@nongnu.org; Thu, 07 Jan 2010 15:27:57 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NSyxV-00048r-Pi for qemu-devel@nongnu.org; Thu, 07 Jan 2010 15:27:57 -0500 Received: from [199.232.76.173] (port=38257 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NSyxV-00048R-IF for qemu-devel@nongnu.org; Thu, 07 Jan 2010 15:27:53 -0500 Received: from mail-fx0-f222.google.com ([209.85.220.222]:33820) by monty-python.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NSyxV-0000ti-0X for qemu-devel@nongnu.org; Thu, 07 Jan 2010 15:27:53 -0500 Received: by fxm22 with SMTP id 22so21243905fxm.2 for ; Thu, 07 Jan 2010 12:27:51 -0800 (PST) Received: from localhost ([127.0.0.1] helo=[192.168.1.2]) by skyserv with esmtp (Exim 4.71) (envelope-from ) id 1NSyxR-0004Ok-5n for qemu-devel@nongnu.org; Thu, 07 Jan 2010 23:27:49 +0300 From: "Igor V. Kovalenko" Date: Thu, 07 Jan 2010 23:27:48 +0300 Message-ID: <20100107201810.16653.85771.stgit@skyserv> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 0/9] sparc64: interrupts and tick timers v1 List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org The following series is a cleanup over previous one. v0 -> v1: post-review changes - dropped patch "clear exception_index with -1 val" (applied) - new patch "change_pstate should have 32bit argument" - cleanups for coding style and hexadecimal output convention - wrpil is no-op for CONFIG_USER_ONLY - restored PIL 15 as non-maskable interrupt level on sparcv8 - check for PSTATE.IE is replaced with call to cpu_interrupts_enabled() - in patch "sparc64: interrupt trap handling" cleaned up change in cpu_exec; since sparc64 does not use CPU_INTERRUPT_TIMER now, corresponding code branch is unchanged --- Igor V. Kovalenko (9): sparc64: change_pstate should have 32bit argument sparc64: trace pstate and global register set changes sparc64: add PIL to cpu state dump sparc64: use helper_wrpil to check pending irq on write sparc64: check for pending irq when pil, pstate or softint is changed sparc64: add macros to deal with softint and timer interrupt sparc64: move cpu_interrupts_enabled to cpu.h sparc64: interrupt trap handling sparc64: reimplement tick timers cpu-exec.c | 28 +++--- hw/sun4u.c | 225 +++++++++++++++++++++++++++++++++++++--------- target-sparc/cpu.h | 27 ++++++ target-sparc/exec.h | 13 --- target-sparc/helper.c | 1 target-sparc/helper.h | 1 target-sparc/op_helper.c | 81 +++++++++++++++-- target-sparc/translate.c | 5 - 8 files changed, 300 insertions(+), 81 deletions(-) -- Kind regards, Igor V. Kovalenko