From: "Igor V. Kovalenko" <igor.v.kovalenko@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 4/9] sparc64: use helper_wrpil to check pending irq on write
Date: Thu, 07 Jan 2010 23:28:10 +0300 [thread overview]
Message-ID: <20100107202810.16653.92198.stgit@skyserv> (raw)
In-Reply-To: <20100107201810.16653.85771.stgit@skyserv>
From: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
---
target-sparc/helper.h | 1 +
target-sparc/op_helper.c | 14 ++++++++++++++
target-sparc/translate.c | 5 +----
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 4002b9e..6f103e7 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -5,6 +5,7 @@ DEF_HELPER_0(rett, void)
DEF_HELPER_1(wrpsr, void, tl)
DEF_HELPER_0(rdpsr, tl)
#else
+DEF_HELPER_1(wrpil, void, tl)
DEF_HELPER_1(wrpstate, void, tl)
DEF_HELPER_0(done, void)
DEF_HELPER_0(retry, void)
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 1d3adef..3d7f64c 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -3303,6 +3303,20 @@ void helper_wrpstate(target_ulong new_state)
change_pstate(new_state & 0xf3f);
}
+void helper_wrpil(target_ulong new_pil)
+{
+#if !defined(CONFIG_USER_ONLY)
+ DPRINTF_PSTATE("helper_wrpil old=%x new=%x\n",
+ env->psrpil, (uint32_t)new_pil);
+
+ env->psrpil = new_pil;
+
+ if (cpu_interrupts_enabled(env)) {
+ cpu_check_irqs(env);
+ }
+#endif
+}
+
void helper_done(void)
{
trap_state* tsptr = cpu_tsptr(env);
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index bf6df50..7e9f0cf 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3371,10 +3371,7 @@ static void disas_sparc_insn(DisasContext * dc)
offsetof(CPUSPARCState, tl));
break;
case 8: // pil
- tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0);
- tcg_gen_st_i32(cpu_tmp32, cpu_env,
- offsetof(CPUSPARCState,
- psrpil));
+ gen_helper_wrpil(cpu_tmp0);
break;
case 9: // cwp
gen_helper_wrcwp(cpu_tmp0);
next prev parent reply other threads:[~2010-01-07 20:28 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-01-07 20:27 [Qemu-devel] [PATCH 0/9] sparc64: interrupts and tick timers v1 Igor V. Kovalenko
2010-01-07 20:27 ` [Qemu-devel] [PATCH 1/9] sparc64: change_pstate should have 32bit argument Igor V. Kovalenko
2010-01-07 20:28 ` [Qemu-devel] [PATCH 2/9] sparc64: trace pstate and global register set changes Igor V. Kovalenko
2010-01-07 20:28 ` [Qemu-devel] [PATCH 3/9] sparc64: add PIL to cpu state dump Igor V. Kovalenko
2010-01-07 20:28 ` Igor V. Kovalenko [this message]
2010-01-07 20:28 ` [Qemu-devel] [PATCH 5/9] sparc64: check for pending irq when pil, pstate or softint is changed Igor V. Kovalenko
2010-01-07 20:28 ` [Qemu-devel] [PATCH 6/9] sparc64: add macros to deal with softint and timer interrupt Igor V. Kovalenko
2010-01-07 20:28 ` [Qemu-devel] [PATCH 7/9] sparc64: move cpu_interrupts_enabled to cpu.h Igor V. Kovalenko
2010-01-07 20:28 ` [Qemu-devel] [PATCH 8/9] sparc64: interrupt trap handling Igor V. Kovalenko
2010-01-07 20:28 ` [Qemu-devel] [PATCH 9/9] sparc64: reimplement tick timers Igor V. Kovalenko
2010-01-08 18:16 ` [Qemu-devel] [PATCH 0/9] sparc64: interrupts and tick timers v1 Blue Swirl
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