From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NZraD-0001T7-Hw for qemu-devel@nongnu.org; Tue, 26 Jan 2010 15:00:17 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1NZraC-0001Sp-0Q for qemu-devel@nongnu.org; Tue, 26 Jan 2010 15:00:17 -0500 Received: from [199.232.76.173] (port=46216 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NZraB-0001Sl-PY for qemu-devel@nongnu.org; Tue, 26 Jan 2010 15:00:15 -0500 Received: from afflict.kos.to ([92.243.29.197]:53648) by monty-python.gnu.org with esmtps (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NZraB-0004lY-9v for qemu-devel@nongnu.org; Tue, 26 Jan 2010 15:00:15 -0500 Date: Tue, 26 Jan 2010 22:00:03 +0200 From: Riku Voipio Subject: Re: [Qemu-devel] [PATCH 4/5] linux-user: Add access to TLS registers Message-ID: <20100126200001.GA8762@aardvark.home> References: <1264521604-2020-1-git-send-email-riku.voipio@iki.fi> <1264521604-2020-5-git-send-email-riku.voipio@iki.fi> <761ea48b1001260827y3fd1c292r6cbcb8740fe89bc6@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <761ea48b1001260827y3fd1c292r6cbcb8740fe89bc6@mail.gmail.com> Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laurent Desnogues Cc: qemu-devel@nongnu.org On Tue, Jan 26, 2010 at 05:27:27PM +0100, Laurent Desnogues wrote: > On Tue, Jan 26, 2010 at 5:00 PM, Riku Voipio wrote= : > > From: Riku Voipio > > > > If you compile applications with gcc -mtp=3Dcp15, __thread > > access's will generate an abort. Implement accessing allowed > > cp15.c13 registers on ARMv6K+ in linux-user. > > > > Signed-off-by: Riku Voipio > > --- > > =C2=A0target-arm/helper.c | =C2=A0 27 ++++++++++++++++++++++++++- > > =C2=A01 files changed, 26 insertions(+), 1 deletions(-) > > > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > index b3aec99..68578ce 100644 > > --- a/target-arm/helper.c > > +++ b/target-arm/helper.c > > @@ -505,13 +505,38 @@ uint32_t HELPER(get_cp)(CPUState *env, uint32_t= insn) > > > > =C2=A0void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t va= l) > > =C2=A0{ > > + =C2=A0 =C2=A0int op2; > > + > > + =C2=A0 =C2=A0op2 =3D (insn >> 5) & 7; > > + =C2=A0 =C2=A0/* Allow write access to CP15 User RW Thread ID Regist= er */ > > + =C2=A0 =C2=A0if (arm_feature (env, ARM_FEATURE_V6K) && ((insn >> 16= ) & 0xf) =3D=3D 13) { > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0switch (op2) { > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0case 2: > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->cp15.c13_tls1 =3D val= ; > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return; > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > > + =C2=A0 =C2=A0} > > =C2=A0 =C2=A0 cpu_abort(env, "cp15 insn %08x\n", insn); > > =C2=A0} > > > > =C2=A0uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) > > =C2=A0{ > > + =C2=A0 =C2=A0int op2; > > + =C2=A0 =C2=A0/* Allow read access to CP15 User RW and RO Thread ID = Registers */ > > + > > + =C2=A0 =C2=A0op2 =3D (insn >> 5) & 7; > > + =C2=A0 =C2=A0if (arm_feature (env, ARM_FEATURE_V6K) && ((insn >> 16= ) & 0xf) =3D=3D 13) { > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0switch (op2) { > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0case 2: > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return env->cp15.c13_tls1; > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0case 3: > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return env->cp15.c13_tls2; > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0default: > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto bad_reg; > > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > > + =C2=A0 =C2=A0} > > +bad_reg: > > =C2=A0 =C2=A0 cpu_abort(env, "cp15 insn %08x\n", insn); > > - =C2=A0 =C2=A0return 0; > > =C2=A0} > > > > =C2=A0/* These should probably raise undefined insn exceptions. =C2=A0= */ > Most of the checks you do here could be done in translate.c. > Wouldn't it be better to do them there? Indeed, thus we could even avoid the helper completly. I just followed th= e the cp15 implementation of system-qemu here.