Re: [Qemu-devel] [PATCH] target-mips: fix CpU exception for coprocessor 0

[Aurelien Jarno <aurelien@aurel32.net>]

On Sat, Feb 20, 2010 at 10:19:09AM -0800, Nathan Froyd wrote:
> When we signal a CpU exception for coprocessor 0, we should indicate
> that it's for coprocessor 0 instead of coprocessor 1.

Thanks applied.

> Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
> ---
>  target-mips/translate.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index dfea6f6..f3522f5 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -830,7 +830,7 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv
>  static inline void check_cp0_enabled(DisasContext *ctx)
>  {
>      if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
> -        generate_exception_err(ctx, EXCP_CpU, 1);
> +        generate_exception_err(ctx, EXCP_CpU, 0);
>  }
>  
>  static inline void check_cp1_enabled(DisasContext *ctx)
> -- 
> 1.6.3.2
> 
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net