From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NlOYd-0002qd-T3 for qemu-devel@nongnu.org; Sat, 27 Feb 2010 10:26:20 -0500 Received: from [199.232.76.173] (port=50657 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NlOYd-0002qM-Bo for qemu-devel@nongnu.org; Sat, 27 Feb 2010 10:26:19 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1NlOYc-0006E3-6r for qemu-devel@nongnu.org; Sat, 27 Feb 2010 10:26:19 -0500 Received: from hall.aurel32.net ([88.191.82.174]:54224) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1NlOYb-0006Dr-TG for qemu-devel@nongnu.org; Sat, 27 Feb 2010 10:26:18 -0500 Date: Sat, 27 Feb 2010 16:26:12 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] target-ppc: fix SPE evcmp* instructions Message-ID: <20100227152612.GD10291@volta.aurel32.net> References: <1266954914-29595-1-git-send-email-froydnj@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1266954914-29595-1-git-send-email-froydnj@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nathan Froyd Cc: qemu-devel@nongnu.org On Tue, Feb 23, 2010 at 11:55:14AM -0800, Nathan Froyd wrote: > The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit > position. Because of this, the SPE evcmp* family of instructions would > store values in the result condition register that were also off by one > bit position. > > Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts. > > Signed-off-by: Nathan Froyd Thanks, applied. > --- > target-ppc/cpu.h | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index d15bba1..63aeb86 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -834,10 +834,10 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) > #define CRF_GT 2 > #define CRF_EQ 1 > #define CRF_SO 0 > -#define CRF_CH (1 << 4) > -#define CRF_CL (1 << 3) > -#define CRF_CH_OR_CL (1 << 2) > -#define CRF_CH_AND_CL (1 << 1) > +#define CRF_CH (1 << CRF_LT) > +#define CRF_CL (1 << CRF_GT) > +#define CRF_CH_OR_CL (1 << CRF_EQ) > +#define CRF_CH_AND_CL (1 << CRF_SO) > > /* XER definitions */ > #define XER_SO 31 > -- > 1.6.3.2 > > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net