From: Aurelien Jarno <aurelien@aurel32.net>
To: qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] Re: Regression: segfault on ARM host
Date: Fri, 5 Mar 2010 21:03:18 +0100 [thread overview]
Message-ID: <20100305200318.GV10291@volta.aurel32.net> (raw)
In-Reply-To: <20100302000529.GO8952@hall.aurel32.net>
On Tue, Mar 02, 2010 at 01:05:29AM +0100, Aurelien Jarno wrote:
> On Mon, Mar 01, 2010 at 11:33:23PM +0100, Paolo Bonzini wrote:
> > On 03/01/2010 10:33 PM, Aurelien Jarno wrote:
> >> While trying to implement setcond on TCG ARM, I have discovered it does
> >> not work anymore. I have bisected this regression to:
> >>
> >> commit 6113d6d3169393c323ac4c82d756a850145a5e7a
> >> Author: Paolo Bonzini<pbonzini@redhat.com>
> >> Date: Fri Jan 15 09:42:09 2010 +0100
> >>
> >> change while to if
> >>
> >> The while loop will be executed exactly 0 or 1 times, depending on
> >> env->exit_request.
> >>
> >> Signed-off-by: Paolo Bonzini<pbonzini@redhat.com>
> >> Signed-off-by: Anthony Liguori<aliguori@us.ibm.com>
> >>
> >> The assertion is actually triggered. When the next patch removing the
> >> assertion is also applied it segfaults instead.
> >
> > Looks like a race. The only piece of logic that is changed by that
> > commit is reverted in the attached patch, can you try it? If it passes,
> > I can resubmit with S-o-b.
>
> Unfortunately it doesn't work.
>
The bug is actually in the ARM backend, I have just send a patch on the
mailing list to fix it.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
prev parent reply other threads:[~2010-03-05 20:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-03-01 21:33 [Qemu-devel] Regression: segfault on ARM host Aurelien Jarno
2010-03-01 22:33 ` [Qemu-devel] " Paolo Bonzini
2010-03-02 0:05 ` Aurelien Jarno
2010-03-05 20:03 ` Aurelien Jarno [this message]
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